Hi Donald,

You could consider the NXP 74HCT9046A as a replacement.  It is an
improved version of 4046.  However, you do need to study the spec sheet
as it is a bit different, but in a good way.

I have included an attached PDF of the spec sheet, if it makes through
the mail list server.

Bill....WB6BNQ

donald collie wrote:

Thankyou Attila. I remember reading a book on PLL theory, recently,writen
by a very knowledgable fellow, but I didnt think to make a copy of his critique of the 4046. I recall that the nub of it was that the 4046 isnt
suitable for some applications because of a design flaw. Perhaps somebody
in this group could explain further.
Thankyou Bill, for the datasheet on the 74HCT9046, and your comments
Cheers!..............................................................................Don
jnr ZL4GX

http://www.avg.com/email-signature?utm_medium=email&utm_source=link&utm_campaign=sig-email&utm_content=webmail
Virus-free.
www.avg.com
http://www.avg.com/email-signature?utm_medium=email&utm_source=link&utm_campaign=sig-email&utm_content=webmail
<#DAB4FAD8-2DD7-40BB-A1B8-4E2AA1F9FDF2>

On Wed, Apr 18, 2018 at 8:28 PM, wb6bnq wb6bnq@cox.net wrote:

Hi Donald,

I've just had this problem - the 'signal' input (p14) to the phase detectors is a 'bodge' linear amplifier built around standard CMOS stages and it doesn’t work right. A resistor around a CMOS inverter was a good old recipe to get a 'linear' amplifier stage but this design appears to have a voltage variable resistor of sorts and it gives very strange results. It is fine if used as a CMOS level i/p stage but its use as an  ac coupled low level i/p is problematic and may need additional loading. Manufacturer's documentation is scarce and I have only seen one reference to the internal design of this stage. There's quite a bit about it in several places on the net.

Regards,
Paul  Reeves      G8GJA

-----Original Message-----
From: time-nuts [mailto:time-nuts-bounces@febo.com] On Behalf Of donald collie
Sent: 18 April 2018 10:40
To: Discussion of precise time and frequency measurement
Subject: Re: [time-nuts] 4046 replacement

Thankyou Attila. I remember reading a book on PLL theory, recently,writen by a very knowledgable fellow, but I didnt think to make a copy of his critique of the 4046. I recall that the nub of it was that the 4046 isnt suitable for some applications because of a design flaw. Perhaps somebody in this group could explain further.
Thankyou Bill, for the datasheet on the 74HCT9046, and your comments Cheers!..............................................................................Don
jnr ZL4GX

http://www.avg.com/email-signature?utm_medium=email&utm_source=link&utm_campaign=sig-email&utm_content=webmail
Virus-free.
www.avg.com
http://www.avg.com/email-signature?utm_medium=email&utm_source=link&utm_campaign=sig-email&utm_content=webmail
<#DAB4FAD8-2DD7-40BB-A1B8-4E2AA1F9FDF2>

On Wed, Apr 18, 2018 at 8:28 PM, wb6bnq wb6bnq@cox.net wrote:

time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.

The tristate phase/freq comparator in the original 4046 had a dead-band problem that caused its gain to vary widely as it approached its normal operating point in a stable loop.  This wasn't so much a 'bug' as it was a consequence of the fact that there's effectively no gain when there's no phase error to correct.

Ulrich Rohde's book indicates that this problem was first documented in 1978 in an EDN article by some authors named Egan and Clark.  Newer PFDs implement the 'antibacklash' logic that Rohde mentions.  If you really must use a 4046, I'd look for a newer version whose data sheet explicitly addresses this problem.  Better still, use a newer part.

Another workaround is to force the PFD to stay out of its dead zone by loading the output lightly, e.g. with a 1M resistor.  You can never compensate for this effect perfectly, though.  You can probably expect some downsides like worse reference suppression.

-- john, KE5FX
Miles Design LLC

There is no dead time issue at all with 4046 PLL's using the built-in XOR
(Type I) phase detector.

There can be a dead-time issue with 4046 PLL's using the built-in type II
(flip-flop) edge detector.

The 74HCT9046A uses current sources instead of voltage sources in its type
II (flip-flop) edge detector to avoid dead-time issues with this phase
detector.

The Type I phase detector was most commonly used in most 4046 narrowband
PLL applications.

The Type II was mostly used for the applications where the VCO had to track
over most of an octave or more than an octave. Most of these Type II
applications were relatively insensitive to dead time. (Otherwise the
phase-nuts 40 years ago would've noticed. Yes you can hear phase noise even
if they didn't have a good systematic way to measure it back then.)

If your original 4046 circuit has been working fine for the past 40 years
(the 4046 must be 40+ years old now) I see no reason to rip it out and
replace it with the newer variant. You may have trouble finding
through-hole (non-surface mount) 74HCT9046A's at this date anyway.

Tim N3QE

On Wed, Apr 18, 2018 at 5:40 AM, donald collie donaldbcollie@gmail.com
wrote:

On 4/18/2018 4:34 AM, John Miles wrote:

The book is incorrect.  A patent issued in 1976 (US4023116A)
covering the Fairchild 11C44 developed by Eric Breeze predates
the EDN article by several years.  I still remember the big
splash the 11C44 made when it was introduced in 1976. The Fairchild
ECL data book had a famous graph comparing it to the MC4044
in the dead zone.  In those days, Fairchild and Motorola
were going head to head.  I worked on a synthesizer in 1975
that used their brand new at the time 11C90 prescaler.

You can still get 11C44's of a sort by ordering NTE974's
that claim to be a replacement.

Rick N6RK

Rick wrote:

The attached graph is the one I remember.  Note that, while the 11C44
was better than the MC4044, neither one was really very linear near zero
error.  Good multichip PFD designs of the era outperformed both of them.

Best regards,

Charles

Hi,

On 04/18/2018 10:57 PM, Charles Steinmetz wrote:

Gardner thrown at them and suggested to use a mixer instead, as it has
better performance.

The real benefit of the 4044 and 4046 lies in that they where CMOS
devices and integrated well with other CMOS devices, and could help to
make designs more compact. If fills a purpose, but does not necessarily
give you optimum performance.

BTW, as you add noise to the signal, much of the behavior of the
triangle or sawtooth shape of the phase-detector average out to that of
a sine, which is no better than that of a mixer, but what happen in the
process is that the phase detector gain changed, and thus the loop
parameters. If you use a mixer, the phase detector gain becomes less
dependent on the S/N and thus a more stable system behavior.

Cheers,
Magnus

On 4/18/2018 3:15 PM, Magnus Danielson wrote:

The original MC4044 is TTL, not CMOS.  There is a CMOS "CD4044"
but it is something completely different, not even a phase detector at all.

Rick N6RK

I filed patent 3,810,234 on Aug 21, 1972. It includes a dual-d pfd with
variable delay in the feedback path to eliminate deadband. The term
deadband is not included in the patent since it did not exist at the time.
The google url is

https://patentimages.storage.googleapis.com/53/fc/f0/26d83e477e999a/US3810234.pdf

The dual-d is items 24 and 26 on page 4. The feedback is item 58, and the
variable delay is item 28 on the same page. It turns out the delay was not
needed in production since there was no deadband when it was shorted out.

I recall finding an article on the dual-d pfd that was earlier than my
patent but I forget where I found it.

Ignore the name Steve Wilson. That is my online name to foil id theft and
malware.

Mike Monett

Sorry, I was mistaken. I explain dead-band on Page 9 of the patent:

"The basic configuration of the phase detector 20 includes two
D-type flip-flops 24 and 26 with feedback to restore both to the
initial state after both have been clocked. A delay 28 in the
feedback path 30 establishes the minimum time that either flip-flop
is in the clocked state, thus establishing a minimum time that
current sources 21a and 21b are switched on. Delay 28 is selected to
insure that both current sources 21a and 21b are first turned fully
on before they are turned off. This feature is necessary to
eliminate dead-band whereby the phase detector 20 does not respond
properly to small phase errors (or time differences) between the two
input signals to the phase detector 20."

This explanation is accurate for symmetrical charge pump delays. The
deadband in the MC4044 is not symmetrical. The DF delay is caused by a
transistor being slow coming out of saturation. This could have been
prevented by applying a Baker clamp around the transistor, or by simply
using diodes to switch the charge pump as was done by CR1 for the UF path.

The transistor in question is Q2 shown on page 5 of the attached MC4044
datasheet.

Also note the DF and UF outputs are shorted together in the datasheet. This
creates a short across VCC on every cycle as both are turned on to reset
the latches.