Discussion and technical support related to USRP, UHD, RFNoC
View all threadsHi,
I have read the datahseet of the AD9361 and I see that we can communicate with the AD9361 by two sort of bus (LVDS or parallel MOS level data).
I would like to know what kind of bus we use with the Ettus B210?! In the schematic online, we can understand that we are using the parallel MOS level?! If we use the LVDS we could be much faster isn it?!
--
Edouard LECLERCQ
Website : http://electronicsprojectsel.blogspot.fr/
Hello Edouard,
Now, I'm no expert in the digital design motivations behind the B2x0
architecture, so if there's anything to add, others may chime in, but
avoiding a longer wait:
You're right; compare our b200.ucf [1]
NET "tx_codec_d<0>" LOC = "T2" | IOSTANDARD = LVCMOS18 ;
NET "tx_codec_d<1>" LOC = "R1" | IOSTANDARD = LVCMOS18 ;
NET "tx_codec_d<2>" LOC = "V2" | IOSTANDARD = LVCMOS18 ;
NET "tx_codec_d<3>" LOC = "N1" | IOSTANDARD = LVCMOS18 ;
NET "tx_codec_d<4>" LOC = "V3" | IOSTANDARD = LVCMOS18 ;
NET "tx_codec_d<5>" LOC = "T1" | IOSTANDARD = LVCMOS18 ;
NET "tx_codec_d<6>" LOC = "W1" | IOSTANDARD = LVCMOS18 ;
NET "tx_codec_d<7>" LOC = "U1" | IOSTANDARD = LVCMOS18 ;
NET "tx_codec_d<8>" LOC = "W3" | IOSTANDARD = LVCMOS18 ;
NET "tx_codec_d<9>" LOC = "U3" | IOSTANDARD = LVCMOS18 ;
NET "tx_codec_d<10>" LOC = "P2" | IOSTANDARD = LVCMOS18 ;
NET "tx_codec_d<11>" LOC = "R3" | IOSTANDARD = LVCMOS18 ;
NET "tx_codec_d*" DRIVE = 2;
However, considering the AD9361 is able to transport the maximum
possible bandwidth over the LVCMOS interface, there's not much to win
increasing the data rate of the data lines.
Best regards,
Marcus
[1]
https://github.com/EttusResearch/fpga/blob/master/usrp3/top/b200/b200.ucf#L60
On 29.12.2015 21:12, Edouard Leclercq via USRP-users wrote:
Hi,
I have read the datahseet of the AD9361 and I see that we can
communicate with the AD9361 by two sort of bus (LVDS or parallel MOS
level data).
I would like to know what kind of bus we use with the Ettus B210?! In
the schematic online, we can understand that we are using the parallel
MOS level?! If we use the LVDS we could be much faster isn it?!
--
Edouard LECLERCQ
Website : http://electronicsprojectsel.blogspot.fr/
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