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Discussion of precise time and frequency measurement

Re: [time-nuts] pps vs. 10 MHz timing

SAIDJACK@aol.com

Fri, Dec 12, 2008 10:12 PM

Hello Matt, Magnus,

unfortunately there will be a phase shift between the 1PPS and the 10MHz
rising edge due to the nature of how we generate the 1PPS pulse from the clean
OCXO 10MHz signal.

But this trade-off allows us to offer the 1PPS phase-shift option via the
SERV:1PPS command.

We can simply shift the 1PPS by 16.66ns steps with the software command,
which would not be possible if we had to align the signal to the 10MHz, 100ns
period.

The system works by multiplying the 10MHz signal up to 60MHz using a PLL,
then using a 60E6-to-1 divider with arbitrary phase alignment (selected by the
user) to generate the clean 1PPS output. This allows a resolution of 16.66ns
on where to place the clean 1PPS using the serv:1pps command.

As Magnus has suggested, if you need a strict phase alignment, then using
FF's to latch the 1PPS rising edge with the 10MHz signal can phase-align the two
signals. Due to metastability being possible, metastable-hardened FF's (from
NXP etc) should be used. Alternatively an external 10E6-to-1 divider could
also be used for this, clocked by the 10MHz signal. There would still be at
least a clock-to-output phase shift when using FPLD's etc to implement this
divider.

BTW: by using the serv:1pps command for the coarse setting, and the GPS
antenna-delay command for fine-setting the user can place the 1PPS pulse anywhere
with 1ns resolution on the Fury GPSDO. The coarse 16.66ns steps will be
instantaneous, the 1ns antenna-delay steps will take some time for the PLL to
shift.

Hope that helps,
bye,
Said

In a message dated 12/12/2008 12:33:25 Pacific Standard Time,
magnus@rubidium.dyndns.org writes:

Matt Ettus skrev:

On my Oscilloquartz GPSDO, the 10 MHz output goes low at very close to
the same time as the 1 PPS output goes high.

On my Fury, the 10 MHz sine wave is just dropping off of its max high
voltage as the 1 PPS goes high. The 10 MHz CMOS output goes high just
shortly before the 1 PPS.

What do other GPSDOs do?

You can expect anything. Some buffers the PPS from the GPS engine and
then make some more or less elaborate 10 MHz training algorithm. Don't
expect rising edges to coinside for all of them.

Clearly, any device trying to latch the 1 PPS signal using the 10 MHz
clock will need to choose which clock edge to use, depending on which
type of GPSDO is used. How is this normally handled?

Hello Matt, Magnus, unfortunately there will be a phase shift between the 1PPS and the 10MHz rising edge due to the nature of how we generate the 1PPS pulse from the clean OCXO 10MHz signal. But this trade-off allows us to offer the 1PPS phase-shift option via the SERV:1PPS command. We can simply shift the 1PPS by 16.66ns steps with the software command, which would not be possible if we had to align the signal to the 10MHz, 100ns period. The system works by multiplying the 10MHz signal up to 60MHz using a PLL, then using a 60E6-to-1 divider with arbitrary phase alignment (selected by the user) to generate the clean 1PPS output. This allows a resolution of 16.66ns on where to place the clean 1PPS using the serv:1pps command. As Magnus has suggested, if you need a strict phase alignment, then using FF's to latch the 1PPS rising edge with the 10MHz signal can phase-align the two signals. Due to metastability being possible, metastable-hardened FF's (from NXP etc) should be used. Alternatively an external 10E6-to-1 divider could also be used for this, clocked by the 10MHz signal. There would still be at least a clock-to-output phase shift when using FPLD's etc to implement this divider. BTW: by using the serv:1pps command for the coarse setting, and the GPS antenna-delay command for fine-setting the user can place the 1PPS pulse anywhere with 1ns resolution on the Fury GPSDO. The coarse 16.66ns steps will be instantaneous, the 1ns antenna-delay steps will take some time for the PLL to shift. Hope that helps, bye, Said In a message dated 12/12/2008 12:33:25 Pacific Standard Time, magnus@rubidium.dyndns.org writes: Matt Ettus skrev: > On my Oscilloquartz GPSDO, the 10 MHz output goes low at very close to > the same time as the 1 PPS output goes high. > > On my Fury, the 10 MHz sine wave is just dropping off of its max high > voltage as the 1 PPS goes high. The 10 MHz CMOS output goes high just > shortly before the 1 PPS. > > What do other GPSDOs do? You can expect anything. Some buffers the PPS from the GPS engine and then make some more or less elaborate 10 MHz training algorithm. Don't expect rising edges to coinside for all of them. > Clearly, any device trying to latch the 1 PPS signal using the 10 MHz > clock will need to choose which clock edge to use, depending on which > type of GPSDO is used. How is this normally handled?

Magnus Danielson

Fri, Dec 12, 2008 11:14 PM

SAIDJACK@aol.com skrev:

Hello Matt, Magnus,

unfortunately there will be a phase shift between the 1PPS and the 10MHz
rising edge due to the nature of how we generate the 1PPS pulse from the clean
OCXO 10MHz signal.

But this trade-off allows us to offer the 1PPS phase-shift option via the
SERV:1PPS command.

We can simply shift the 1PPS by 16.66ns steps with the software command,
which would not be possible if we had to align the signal to the 10MHz, 100ns
period.

Being able to fine-tune PPS-10 MHz phase relationship on the output is
certainly a good thing.

Some have very tight requirements for this relationship, but it seems to
me that they overspec it since they do not really know how things work
and it is easy to verify. On the other hand, for some equipment I
haven't seen any reasnoble specs at all on the inputs. Seems they have
designed to match what their GPS gives them, whatever that is.

Sweet. Personally I did it a bit differently, but that's another thing.
There are many things to implement the same thing.

You can use a FPLD for the counter state, but then use a good DFF to
clock the state into a low jitter form. Since both is running of the
same clock, just ensuring propper setup and hold times at the DFF input
would suffice to ensure it is not be unstable. Just traditional engineering.

You really can't sync up some PPSes to the 10 MHz by simple DFFs since
the variations may be more than 100 ns during some phases of the
training and holdover shifts. The PPS output should always be generated
using the 10 MHz such as they have a stable phase-relationship. The
generated PPS is then compared to the source PPS and controlled phase
adjustments should be done.

Cheers,
Magnus

SAIDJACK@aol.com skrev: > Hello Matt, Magnus, > > unfortunately there will be a phase shift between the 1PPS and the 10MHz > rising edge due to the nature of how we generate the 1PPS pulse from the clean > OCXO 10MHz signal. > > But this trade-off allows us to offer the 1PPS phase-shift option via the > SERV:1PPS command. > > We can simply shift the 1PPS by 16.66ns steps with the software command, > which would not be possible if we had to align the signal to the 10MHz, 100ns > period. Being able to fine-tune PPS-10 MHz phase relationship on the output is certainly a good thing. Some have very tight requirements for this relationship, but it seems to me that they overspec it since they do not really know how things work and it is easy to verify. On the other hand, for some equipment I haven't seen any reasnoble specs at all on the inputs. Seems they have designed to match what their GPS gives them, whatever that is. > The system works by multiplying the 10MHz signal up to 60MHz using a PLL, > then using a 60E6-to-1 divider with arbitrary phase alignment (selected by the > user) to generate the clean 1PPS output. This allows a resolution of 16.66ns > on where to place the clean 1PPS using the serv:1pps command. Sweet. Personally I did it a bit differently, but that's another thing. There are many things to implement the same thing. > As Magnus has suggested, if you need a strict phase alignment, then using > FF's to latch the 1PPS rising edge with the 10MHz signal can phase-align the two > signals. Due to metastability being possible, metastable-hardened FF's (from > NXP etc) should be used. Alternatively an external 10E6-to-1 divider could > also be used for this, clocked by the 10MHz signal. There would still be at > least a clock-to-output phase shift when using FPLD's etc to implement this > divider. You can use a FPLD for the counter state, but then use a good DFF to clock the state into a low jitter form. Since both is running of the same clock, just ensuring propper setup and hold times at the DFF input would suffice to ensure it is not be unstable. Just traditional engineering. You really can't sync up some PPSes to the 10 MHz by simple DFFs since the variations may be more than 100 ns during some phases of the training and holdover shifts. The PPS output should always be generated using the 10 MHz such as they have a stable phase-relationship. The generated PPS is then compared to the source PPS and controlled phase adjustments should be done. Cheers, Magnus