Hi, I have b200 mini and by reading registers I figured out that it is using CMOS for digital interface between ad9361 and BBP. Is there a way to make it use LVDS? For example, an FPGA image that could do this? I am using GNU radio and UHD to program the board, what other modifications in the software I will need to support LVDS if possible? Thanks, Ahmed

On 2022-05-18 15:42, ahamza1982@gmail.com wrote: > > Hi, > > > I have b200 mini and by reading registers I figured out that it is > using CMOS for digital interface between ad9361 and BBP. > > Is there a way to make it use LVDS? > > For example, an FPGA image that could do this? > > I am using GNU radio and UHD to program the board, what other > modifications in the software I will need to support LVDS if possible? > > > Thanks, > > Ahmed > > A very similar question was asked on this list about one week ago. The basic answer is that this was tried, years ago, and the FPGA couldn't meet the S/H  timing for the faster LVDS interface. So,the CMOS interface is used. Now, while it MAY be the case that "having another look" might yield the ability to use the LVDS interface, there is not an FPGA image "in the wild"   that allows this.

On Wed, May 18, 2022 at 4:20 PM Marcus D. Leech <patchvonbraun@gmail.com> wrote: > On 2022-05-18 15:42, ahamza1982@gmail.com wrote: > > > > Hi, > > > > > > I have b200 mini and by reading registers I figured out that it is > > using CMOS for digital interface between ad9361 and BBP. > > > > Is there a way to make it use LVDS? > > > > For example, an FPGA image that could do this? > > > > I am using GNU radio and UHD to program the board, what other > > modifications in the software I will need to support LVDS if possible? > > > > > > Thanks, > > > > Ahmed > > > > > A very similar question was asked on this list about one week ago. The > basic answer is that this was tried, years ago, and the FPGA couldn't > meet the S/H > timing for the faster LVDS interface. So,the CMOS interface is used. > I believe this is a slightly different issue. The previous issue was the LVDS interface is already used, but the faster 61.44 Msps was not supported for dual channel operations. The FPGA used is a Zynq device on the E320. The interface here is CMOS and talking to a Spartan 6 device with a bank voltage of 1.8v. This inherently makes it impossible to program the FPGA for those pins to utilize LVDS. Brian

Many thanks for both of you for the detailed answer. Best regards, Ahmed

On 2022-05-18 16:28, Brian Padalino wrote: > > I believe this is a slightly different issue.  The previous issue was > the LVDS interface is already used, but the faster 61.44 Msps was not > supported for dual channel operations.  The FPGA used is a Zynq device > on the E320. Thanks for having a better memory :) > > The interface here is CMOS and talking to a Spartan 6 device with a > bank voltage of 1.8v.  This inherently makes it impossible to program > the FPGA for those pins to utilize LVDS. > > Thanks, I only "play hardware guy" in very limited contexts.   Yeah, it looks like 2.5V (or hair lower) is the lowest common-mode voltage supported by LVDS.