I understood the picture did not make it. Attached now Erik. On 7-2-2025 16:46, Erik Kaashoek wrote: > Dana, > > Hope the picture makes it this way > This is cycle time (vertical axis, in seconds), measured with 40 ps > resolution, of about 3500 individual cycles (horizontal axis) of the > output clock set to 10 kHz. > It seems the cycle time is set to the integer divide of the system > clock closest to the requested output frequency. > Every 460 (or sometimes 470) cycles a individual output cycle is > stretched (or shortened) with about 8 ns to move the average output > frequency to the requested output frequency. > The number of cycle insertions/deletions depend on the fractional > difference between integer divided system clock and the requested > clock. If these are very close you could get a hanging bridge I guess > as there is no need to insert a cycle for a long time. > >