vivado_utils::close_batch_project

Hi everybody, I'm playing around with RFNoC and I wanted to generate a bitstream with 2 x DDC, 2 x DUC and 1 x FFT. In order to do so, I used the following command: ./uhd_image_builder.py ddc ddc duc duc fft -d x310 -t X310_RFNOC_HG -m 5 --fill-with-fifos It seems like it was successful as the output of that command was: %------------------------------------------------------------------------------------------------------------------------------ Creating bitstream... Writing bitstream /home/zz4fap/rfnoc/src/uhd-fpga/usrp3/top/x300/build-X310_RFNOC_HG/x300.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Common 17-83] Releasing license: Implementation write_bitstream: Time (s): cpu = 00:03:28 ; elapsed = 00:03:02 . Memory (MB): peak = 6782.297 ; gain = 140.734 ; free physical = 2356 ; free virtual = 23109 BUILDER: Writing config bitstream BUILDER: Writing debug probes BUILDER: Writing export report report_utilization: Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 6782.297 ; gain = 0.000 ; free physical = 2339 ; free virtual = 23107 INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs report_timing_summary: Time (s): cpu = 00:00:29 ; elapsed = 00:00:10 . Memory (MB): peak = 6782.301 ; gain = 0.004 ; free physical = 2364 ; free virtual = 23125 # vivado_utils::close_batch_project BUILDER: Closing project ****** Webtalk v2015.4.2 (64-bit) **** SW Build 1494164 on Fri Feb 26 04:18:54 MST 2016 **** IP Build 1491208 on Wed Feb 24 03:25:39 MST 2016 ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. source /home/zz4fap/rfnoc/src/uhd-fpga/usrp3/top/x300/build-X310_RFNOC_HG/.Xil/Vivado-3734-imecdesktop/webtalk/labtool_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Thu Feb 23 12:41:12 2017... close_project: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 6782.301 ; gain = 0.000 ; free physical = 2361 ; free virtual = 23122 INFO: [Common 17-206] Exiting Vivado at Thu Feb 23 12:41:12 2017... make[1]: Leaving directory `/home/zz4fap/rfnoc/src/uhd-fpga/usrp3/top/x300' Exporting bitstream files... Generating LVBITX... Exporting build report... Build DONE ... X310_RFNOC_HG %------------------------------------------------------------------------------------------------------------------------------ After the bitstream was created I renamed it as follows mv ./src/uhd-fpga/usrp3/top/x300/build-X310_RFNOC_HG/x300.bit ./src/uhd-fpga/usrp3/top/x300/build-X310_RFNOC_HG/zz4fap_x310_rfnoc_HG.bit Next, I ran the image loader pointing to my new bitstream and got the message saying the new bitstream is larger than expected. %------------------------------------------------------------------------------------------------------------------------------ ./rfnoc$ uhd_image_loader --args "type=x300,addr=192.168.10.2" --fpga-path ./src/uhd-fpga/usrp3/top/x300/build-X310_RFNOC_HG/zz4fap_x310_rfnoc_HG.bit linux; GNU C++ version 4.8.4; Boost_105400; UHD_4.0.0.rfnoc-devel-211-g2cf80a69 Error: RuntimeError: The specified FPGA image is too large: 15878034 vs. 15878032 %------------------------------------------------------------------------------------------------------------------------------ Follows the output of the "uhd_find_devices" command %------------------------------------------------------------------------------------------------------------------------------ linux; GNU C++ version 4.8.4; Boost_105400; UHD_4.0.0.rfnoc-devel-211-g2cf80a69 -------------------------------------------------- -- UHD Device 0 -------------------------------------------------- Device Address: serial: 30D1714 addr: 192.168.10.2 fpga: HG name: product: X310 type: x300 %------------------------------------------------------------------------------------------------------------------------------ Could someone help me with that, please? Kind Regards, Felipe Augusto