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Discussion and technical support related to USRP, UHD, RFNoC
View all threadsCan X310 support sample rate of 12.8e6?
Dear all,
We are developing an application with sample rate 12.8MHz and have tested successfully with B210.
Now, we are using X310 to run the application, and find that it can not support 12.8MHz sample rate.
For B210, we set master clock rate 25.6MHz, and get 12.8MHz sample rate.
But for X310, it indicates that 25.6MHz master clock rate is invalid:
Error: RuntimeError: Invalid master clock rate: 25.60 MHz.
Valid master clock rates when using a 10.000000 MHz reference clock are:
120 MHz, 184.32 MHz and 200 MHz.
When we choose the master clock rate to 200MHz, we only get a 12.5MHz sample rate.
$ sudo ./benchmark_rate --rx_rate 12.8e6
linux; GNU C++ version 4.8.4; Boost_105400; UHD_3.11.0.git-28-gc66cb1ba
Creating the usrp device with: ...
-- X300 initialization sequence...
-- Determining maximum frame size... 8000 bytes.
-- Setup basic communication...
-- Loading values from EEPROM...
-- Setup RF frontend clocking...
-- Radio 1x clock:200
-- [DMA FIFO] Running BIST for FIFO 0... pass (Throughput: 1176.2MB/s)
-- [DMA FIFO] Running BIST for FIFO 1... pass (Throughput: 1182.1MB/s)
-- [RFNoC Radio] Performing register loopback test... pass
-- [RFNoC Radio] Performing register loopback test... pass
-- [RFNoC Radio] Performing register loopback test... pass
-- [RFNoC Radio] Performing register loopback test... pass
-- Performing timer loopback test... pass
-- Performing timer loopback test... pass
Using Device: Single USRP:
Device: X-Series Device
Mboard 0: X310
RX Channel: 0
RX DSP: 0
RX Dboard: A
RX Subdev: UBX RX
RX Channel: 1
RX DSP: 0
RX Dboard: B
RX Subdev: UBX RX
TX Channel: 0
TX DSP: 0
TX Dboard: A
TX Subdev: UBX TX
TX Channel: 1
TX DSP: 0
TX Dboard: B
TX Subdev: UBX TX
Setting device timestamp to 0...
UHD Warning:
The hardware does not support the requested RX sample rate:
Target sample rate: 12.800000 MSps
Actual sample rate: 12.500000 MSps
UHD Warning:
The hardware does not support the requested RX sample rate:
Target sample rate: 12.800000 MSps
Actual sample rate: 12.500000 MSps
Testing receive rate 12.500000 Msps on 1 channels
Can anybody tell us how to support a sample rate of 12.8MHz?
Thank you very much.
Best regards,
Ligang Liu
//////////////////////////////////// this is the result of uhd_usrp_probe //////////////////////////////////
$ uhd_usrp_probe
linux; GNU C++ version 4.8.4; Boost_105400; UHD_3.11.0.git-28-gc66cb1ba
-- X300 initialization sequence...
-- Determining maximum frame size... 8000 bytes.
-- Setup basic communication...
-- Loading values from EEPROM...
-- Setup RF frontend clocking...
-- Radio 1x clock:200
-- [DMA FIFO] Running BIST for FIFO 0... pass (Throughput: 1180.8MB/s)
-- [DMA FIFO] Running BIST for FIFO 1... pass (Throughput: 1180.0MB/s)
-- [RFNoC Radio] Performing register loopback test... pass
-- [RFNoC Radio] Performing register loopback test... pass
-- [RFNoC Radio] Performing register loopback test... pass
-- [RFNoC Radio] Performing register loopback test... pass
-- Performing timer loopback test... pass
-- Performing timer loopback test... pass
/
| Device: X-Series Device
| _____________________________________________________
| /
| | Mboard: X310
| | revision: 8
| | revision_compat: 7
| | product: 30818
| | mac-addr0: 00:80:2f:25:06:12
| | mac-addr1: 00:80:2f:25:06:13
| | gateway: 192.168.10.1
| | ip-addr0: 192.168.10.2
| | subnet0: 255.255.255.0
| | ip-addr1: 192.168.20.2
| | subnet1: 255.255.255.0
| | ip-addr2: 192.168.30.2
| | subnet2: 255.255.255.0
| | ip-addr3: 192.168.40.2
| | subnet3: 255.255.255.0
| | serial: 30D2D9F
| | FW Version: 5.0
| | FPGA Version: 33.0
| | RFNoC capable: Yes
| |
| | Time sources: internal, external, gpsdo
| | Clock sources: internal, external, gpsdo
| | Sensors: ref_locked
| | _____________________________________________________
| | /
| | | RX Dboard: A
| | | ID: UBX-160 v1 (0x007a)
| | | Serial: 30BA655
| | | _____________________________________________________
| | | /
| | | | RX Frontend: 0
| | | | Name: UBX RX
| | | | Antennas: TX/RX, RX2, CAL
| | | | Sensors: lo_locked
| | | | Freq range: 10.000 to 6000.000 MHz
| | | | Gain range PGA0: 0.0 to 31.5 step 0.5 dB
| | | | Bandwidth range: 160000000.0 to 160000000.0 step 0.0 Hz
| | | | Connection Type: IQ
| | | | Uses LO offset: No
| | | _____________________________________________________
| | | /
| | | | RX Codec: A
| | | | Name: ads62p48
| | | | Gain range digital: 0.0 to 6.0 step 0.5 dB
| | _____________________________________________________
| | /
| | | RX Dboard: B
| | | ID: UBX-160 v1 (0x007a)
| | | Serial: 30CF910
| | | _____________________________________________________
| | | /
| | | | RX Frontend: 0
| | | | Name: UBX RX
| | | | Antennas: TX/RX, RX2, CAL
| | | | Sensors: lo_locked
| | | | Freq range: 10.000 to 6000.000 MHz
| | | | Gain range PGA0: 0.0 to 31.5 step 0.5 dB
| | | | Bandwidth range: 160000000.0 to 160000000.0 step 0.0 Hz
| | | | Connection Type: IQ
| | | | Uses LO offset: No
| | | _____________________________________________________
| | | /
| | | | RX Codec: B
| | | | Name: ads62p48
| | | | Gain range digital: 0.0 to 6.0 step 0.5 dB
| | _____________________________________________________
| | /
| | | TX Dboard: A
| | | ID: UBX-160 v1 (0x0079)
| | | Serial: 30BA655
| | | _____________________________________________________
| | | /
| | | | TX Frontend: 0
| | | | Name: UBX TX
| | | | Antennas: TX/RX, CAL
| | | | Sensors: lo_locked
| | | | Freq range: 10.000 to 6000.000 MHz
| | | | Gain range PGA0: 0.0 to 31.5 step 0.5 dB
| | | | Bandwidth range: 160000000.0 to 160000000.0 step 0.0 Hz
| | | | Connection Type: QI
| | | | Uses LO offset: No
| | | _____________________________________________________
| | | /
| | | | TX Codec: A
| | | | Name: ad9146
| | | | Gain Elements: None
| | _____________________________________________________
| | /
| | | TX Dboard: B
| | | ID: UBX-160 v1 (0x0079)
| | | Serial: 30CF910
| | | _____________________________________________________
| | | /
| | | | TX Frontend: 0
| | | | Name: UBX TX
| | | | Antennas: TX/RX, CAL
| | | | Sensors: lo_locked
| | | | Freq range: 10.000 to 6000.000 MHz
| | | | Gain range PGA0: 0.0 to 31.5 step 0.5 dB
| | | | Bandwidth range: 160000000.0 to 160000000.0 step 0.0 Hz
| | | | Connection Type: QI
| | | | Uses LO offset: No
| | | _____________________________________________________
| | | /
| | | | TX Codec: B
| | | | Name: ad9146
| | | | Gain Elements: None
| | _____________________________________________________
| | /
| | | RFNoC blocks on this device:
| | |
| | | * DmaFIFO_0
| | | * Radio_0
| | | * Radio_1
| | | * DDC_0
| | | * DDC_1
| | | * DUC_0
| | | * DUC_1
On 02/15/2017 10:24 PM, ligang.liu--- via USRP-users wrote:
Dear all,
We are developing an application with sample rate 12.8MHz and have
tested successfully with B210.
Now, we are using X310 to run the application, and find that it can
not support 12.8MHz sample rate.
For B210, we set master clock rate 25.6MHz, and get 12.8MHz sample rate.
But for X310, it indicates that 25.6MHz master clock rate is invalid:
The X310 supports strict-integer decimation, so, you can only get sample
rates that are proper integer fractions of the clock-rates shown, and
you're much better off sticking with a master-clock of 200MHz. Which
means the closest rate is 12.5e6. If 12.8Msps is very important in your
application, then you should consider resampling on the software side.
Error: RuntimeError: Invalid master clock rate: 25.60 MHz.
Valid master clock rates when using a 10.000000 MHz reference clock are:
120 MHz, 184.32 MHz and 200 MHz.
When we choose the master clock rate to 200MHz, we only get a 12.5MHz
sample rate.
$ sudo ./benchmark_rate --rx_rate 12.8e6
linux; GNU C++ version 4.8.4; Boost_105400; UHD_3.11.0.git-28-gc66cb1ba
Creating the usrp device with: ...
-- X300 initialization sequence...
-- Determining maximum frame size... 8000 bytes.
-- Setup basic communication...
-- Loading values from EEPROM...
-- Setup RF frontend clocking...
-- Radio 1x clock:200
-- [DMA FIFO] Running BIST for FIFO 0... pass (Throughput: 1176.2MB/s)
-- [DMA FIFO] Running BIST for FIFO 1... pass (Throughput: 1182.1MB/s)
-- [RFNoC Radio] Performing register loopback test... pass
-- [RFNoC Radio] Performing register loopback test... pass
-- [RFNoC Radio] Performing register loopback test... pass
-- [RFNoC Radio] Performing register loopback test... pass
-- Performing timer loopback test... pass
-- Performing timer loopback test... pass
Using Device: Single USRP:
Device: X-Series Device
Mboard 0: X310
RX Channel: 0
RX DSP: 0
RX Dboard: A
RX Subdev: UBX RX
RX Channel: 1
RX DSP: 0
RX Dboard: B
RX Subdev: UBX RX
TX Channel: 0
TX DSP: 0
TX Dboard: A
TX Subdev: UBX TX
TX Channel: 1
TX DSP: 0
TX Dboard: B
TX Subdev: UBX TX
Setting device timestamp to 0...
UHD Warning:
The hardware does not support the requested RX sample rate:
Target sample rate: 12.800000 MSps
Actual sample rate: 12.500000 MSps
UHD Warning:
The hardware does not support the requested RX sample rate:
Target sample rate: 12.800000 MSps
Actual sample rate: 12.500000 MSps
Testing receive rate 12.500000 Msps on 1 channels
Can anybody tell us how to support a sample rate of 12.8MHz?
Thank you very much.
Best regards,
Ligang Liu
//////////////////////////////////// this is the result of
uhd_usrp_probe //////////////////////////////////
$ uhd_usrp_probe
linux; GNU C++ version 4.8.4; Boost_105400; UHD_3.11.0.git-28-gc66cb1ba
-- X300 initialization sequence...
-- Determining maximum frame size... 8000 bytes.
-- Setup basic communication...
-- Loading values from EEPROM...
-- Setup RF frontend clocking...
-- Radio 1x clock:200
-- [DMA FIFO] Running BIST for FIFO 0... pass (Throughput: 1180.8MB/s)
-- [DMA FIFO] Running BIST for FIFO 1... pass (Throughput: 1180.0MB/s)
-- [RFNoC Radio] Performing register loopback test... pass
-- [RFNoC Radio] Performing register loopback test... pass
-- [RFNoC Radio] Performing register loopback test... pass
-- [RFNoC Radio] Performing register loopback test... pass
-- Performing timer loopback test... pass
-- Performing timer loopback test... pass
/
| Device: X-Series Device
| _____________________________________________________
| /
| | Mboard: X310
| | revision: 8
| | revision_compat: 7
| | product: 30818
| | mac-addr0: 00:80:2f:25:06:12
| | mac-addr1: 00:80:2f:25:06:13
| | gateway: 192.168.10.1
| | ip-addr0: 192.168.10.2
| | subnet0: 255.255.255.0
| | ip-addr1: 192.168.20.2
| | subnet1: 255.255.255.0
| | ip-addr2: 192.168.30.2
| | subnet2: 255.255.255.0
| | ip-addr3: 192.168.40.2
| | subnet3: 255.255.255.0
| | serial: 30D2D9F
| | FW Version: 5.0
| | FPGA Version: 33.0
| | RFNoC capable: Yes
| |
| | Time sources: internal, external, gpsdo
| | Clock sources: internal, external, gpsdo
| | Sensors: ref_locked
| | _____________________________________________________
| | /
| | | RX Dboard: A
| | | ID: UBX-160 v1 (0x007a)
| | | Serial: 30BA655
| | | _____________________________________________________
| | | /
| | | | RX Frontend: 0
| | | | Name: UBX RX
| | | | Antennas: TX/RX, RX2, CAL
| | | | Sensors: lo_locked
| | | | Freq range: 10.000 to 6000.000 MHz
| | | | Gain range PGA0: 0.0 to 31.5 step 0.5 dB
| | | | Bandwidth range: 160000000.0 to 160000000.0 step 0.0 Hz
| | | | Connection Type: IQ
| | | | Uses LO offset: No
| | | _____________________________________________________
| | | /
| | | | RX Codec: A
| | | | Name: ads62p48
| | | | Gain range digital: 0.0 to 6.0 step 0.5 dB
| | _____________________________________________________
| | /
| | | RX Dboard: B
| | | ID: UBX-160 v1 (0x007a)
| | | Serial: 30CF910
| | | _____________________________________________________
| | | /
| | | | RX Frontend: 0
| | | | Name: UBX RX
| | | | Antennas: TX/RX, RX2, CAL
| | | | Sensors: lo_locked
| | | | Freq range: 10.000 to 6000.000 MHz
| | | | Gain range PGA0: 0.0 to 31.5 step 0.5 dB
| | | | Bandwidth range: 160000000.0 to 160000000.0 step 0.0 Hz
| | | | Connection Type: IQ
| | | | Uses LO offset: No
| | | _____________________________________________________
| | | /
| | | | RX Codec: B
| | | | Name: ads62p48
| | | | Gain range digital: 0.0 to 6.0 step 0.5 dB
| | _____________________________________________________
| | /
| | | TX Dboard: A
| | | ID: UBX-160 v1 (0x0079)
| | | Serial: 30BA655
| | | _____________________________________________________
| | | /
| | | | TX Frontend: 0
| | | | Name: UBX TX
| | | | Antennas: TX/RX, CAL
| | | | Sensors: lo_locked
| | | | Freq range: 10.000 to 6000.000 MHz
| | | | Gain range PGA0: 0.0 to 31.5 step 0.5 dB
| | | | Bandwidth range: 160000000.0 to 160000000.0 step 0.0 Hz
| | | | Connection Type: QI
| | | | Uses LO offset: No
| | | _____________________________________________________
| | | /
| | | | TX Codec: A
| | | | Name: ad9146
| | | | Gain Elements: None
| | _____________________________________________________
| | /
| | | TX Dboard: B
| | | ID: UBX-160 v1 (0x0079)
| | | Serial: 30CF910
| | | _____________________________________________________
| | | /
| | | | TX Frontend: 0
| | | | Name: UBX TX
| | | | Antennas: TX/RX, CAL
| | | | Sensors: lo_locked
| | | | Freq range: 10.000 to 6000.000 MHz
| | | | Gain range PGA0: 0.0 to 31.5 step 0.5 dB
| | | | Bandwidth range: 160000000.0 to 160000000.0 step 0.0 Hz
| | | | Connection Type: QI
| | | | Uses LO offset: No
| | | _____________________________________________________
| | | /
| | | | TX Codec: B
| | | | Name: ad9146
| | | | Gain Elements: None
| | _____________________________________________________
| | /
| | | RFNoC blocks on this device:
| | |
| | | * DmaFIFO_0
| | | * Radio_0
| | | * Radio_1
| | | * DDC_0
| | | * DDC_1
| | | * DUC_0
| | | * DUC_1
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