[Context is maybe(?) withdrawing the proposal to stop keeping time on the US
power line.]
wb4gcs@wb4gcs.org said:
Since then, large amounts of generation (primarily coal) has been shut
down, so I was not at all surprised by the request.
I missed the announcement that the request was withdrawn, and actually
thought it had been approved and enacted -- all my line-frequency based
clocks are now erratic and not very accurate.
I could easily be wrong on the withdrawing part. I haven't seen any recent
comments either way.
Where are you located? Did you notice when your clocks started acting
erratic? Do you have any solid data?
I have 2 old, synchronous, line clocks (stove and clock-radio). They seem to
be working normally, but I don't pay a lot of attention to how accurate they
are.
I'm in Silicon Valley. I do monitor the line with a typical time-nut setup.
That's using the Linux PPS stuff to count cycles. Here is an updated graph
covering the last 12 weeks.
http://www.megapathdsl.net/~hmurray/time-nuts/60Hz/Dec-2013.png
The 0 on the left is arbitrary. Peak-to-peak is 15 seconds. So if I set my
mechanical clock correctly, even at the worst time, it would still be within
15 seconds of correct.
That's from counting cycles and dividing by 60. A single cycle is a big
event. Off by one is easy to spot if you look at the right graph. Here is a
sample of a glitch:
http://www.megapathdsl.net/~hmurray/time-nuts/60Hz/60Hz-2014-Feb-20-pick.png
I've only seen one event where a cycle was picked, none for dropped. I might
have missed something interesting. Look at the longer graph above. It's
pretty clear I haven't missed a huge pattern either way.
I saw one comment (don't remember where) that the problem was that the power
companies had to file a lot of paperwork whenever the line frequency dipped
below X. (I don't remember the numbers.) If they were running slow, (say
targeting 59.98) to catch up for running too fast, and an event that dropped
the frequency happened, it was much more likely to trigger the paperwork.
(Seems like they should fix the paperwork-filing rules to allow for that case, but maybe it's more complicated than I can see.)
This is what initiated the 2003
blackout in parts of the US & Canada. A utility had a paucity of reactive
generation on a day with large reactive load, and one of its generators
tripped on over-excitation to prevent damage to the generator and voltage
regulator. This initiated the cascading events that left many in the dark.
(The Joint US/Canada task force on that event is a /fascinating/ read!)
Do you have a URL?
In the late 70's there was a big blackout in NYC. I remember reading the IEEE article on it. I don't remember any frequency graphs. Did they archive that sort of data back then? The deal was that an important line bringing power in to NYC was knocked out by lightning. Power lines have several load capacities, depending on time. Thus they can carry X forever, X+x for a half hour, and X+xx for 5 minutes. A line from Long Island was carrying it's 5 minute rating for way more than 5 minutes. Somebody in the control room had their thumb on the "shut up" button. They knew that line was a critical resource, but they couldn't shift any load. Eventually, it sagged enough to hit a tree. Then that line when out and so did all of NYC. (That's my memory from 35 years ago.)
Blackouts:
http://en.wikipedia.org/wiki/Northeast_blackout_of_1965
http://en.wikipedia.org/wiki/New_York_City_blackout_of_1977
http://en.wikipedia.org/wiki/Northeast_blackout_of_2003
http://en.wikipedia.org/wiki/List_of_major_power_outages
From 1965:
the same song recordings played at normal speed reveal that approximately six minutes before blackout the line frequency was 56 Hz, and just two minutes before the blackout that frequency dropped to 51 Hz.
51Hz ??!! Wow. It would be interesting to see that on a graph.
--
These are my opinions. I hate spam.
Hal:
Here's a url for the task-force report:
http://energy.gov/oe/downloads/us-canada-power-system-outage-task-force-final-report-implementation-task-force
I live near Pittsburgh, PA. I think there is ZERO interconnection
between PJM (grid operator we're on) and yours (forgot the name).
INcidentally, if you read the report, you'll see some incompetence, bad
decisions, and bad management in the 2003 blackout. Only reason we
didn't go dark here is because PJM saw what was happening in Cleveland
and cut them off. (Reminding me of one night on a certain ship in the
late 70's, when one plant was getting unstable and the other plant cut
them off -- half of ship went dark/lost propulsion, but not the whole ship!)
I do not remember when my clocks started acting up; it WAS after the
announcement of the relaxation (or requested relaxation).
I have read about the NY blackout you describe in IEEE pubs (I'm a
member of the power energy society) but don't remember much detail.
All the best,
Jim
wb4gcs@amat.org
On 3/13/2014 2:17 AM, Hal Murray wrote:
[Context is maybe(?) withdrawing the proposal to stop keeping time on the US
power line.]
wb4gcs@wb4gcs.org said:
Since then, large amounts of generation (primarily coal) has been shut
down, so I was not at all surprised by the request.
I missed the announcement that the request was withdrawn, and actually
thought it had been approved and enacted -- all my line-frequency based
clocks are now erratic and not very accurate.
I could easily be wrong on the withdrawing part. I haven't seen any recent
comments either way.
Where are you located? Did you notice when your clocks started acting
erratic? Do you have any solid data?
I have 2 old, synchronous, line clocks (stove and clock-radio). They seem to
be working normally, but I don't pay a lot of attention to how accurate they
are.
I'm in Silicon Valley. I do monitor the line with a typical time-nut setup.
That's using the Linux PPS stuff to count cycles. Here is an updated graph
covering the last 12 weeks.
http://www.megapathdsl.net/~hmurray/time-nuts/60Hz/Dec-2013.png
The 0 on the left is arbitrary. Peak-to-peak is 15 seconds. So if I set my
mechanical clock correctly, even at the worst time, it would still be within
15 seconds of correct.
That's from counting cycles and dividing by 60. A single cycle is a big
event. Off by one is easy to spot if you look at the right graph. Here is a
sample of a glitch:
http://www.megapathdsl.net/~hmurray/time-nuts/60Hz/60Hz-2014-Feb-20-pick.png
I've only seen one event where a cycle was picked, none for dropped. I might
have missed something interesting. Look at the longer graph above. It's
pretty clear I haven't missed a huge pattern either way.
I saw one comment (don't remember where) that the problem was that the power
companies had to file a lot of paperwork whenever the line frequency dipped
below X. (I don't remember the numbers.) If they were running slow, (say
targeting 59.98) to catch up for running too fast, and an event that dropped
the frequency happened, it was much more likely to trigger the paperwork.
(Seems like they should fix the paperwork-filing rules to allow for that case, but maybe it's more complicated than I can see.)
This is what initiated the 2003
blackout in parts of the US & Canada. A utility had a paucity of reactive
generation on a day with large reactive load, and one of its generators
tripped on over-excitation to prevent damage to the generator and voltage
regulator. This initiated the cascading events that left many in the dark.
(The Joint US/Canada task force on that event is a /fascinating/ read!)
Do you have a URL?
In the late 70's there was a big blackout in NYC. I remember reading the IEEE article on it. I don't remember any frequency graphs. Did they archive that sort of data back then? The deal was that an important line bringing power in to NYC was knocked out by lightning. Power lines have several load capacities, depending on time. Thus they can carry X forever, X+x for a half hour, and X+xx for 5 minutes. A line from Long Island was carrying it's 5 minute rating for way more than 5 minutes. Somebody in the control room had their thumb on the "shut up" button. They knew that line was a critical resource, but they couldn't shift any load. Eventually, it sagged enough to hit a tree. Then that line when out and so did all of NYC. (That's my memory from 35 years ago.)
Blackouts:
http://en.wikipedia.org/wiki/Northeast_blackout_of_1965
http://en.wikipedia.org/wiki/New_York_City_blackout_of_1977
http://en.wikipedia.org/wiki/Northeast_blackout_of_2003
http://en.wikipedia.org/wiki/List_of_major_power_outages
From 1965:
the same song recordings played at normal speed reveal that approximately six minutes before blackout the line frequency was 56 Hz, and just two minutes before the blackout that frequency dropped to 51 Hz.
51Hz ??!! Wow. It would be interesting to see that on a graph.
This email is free from viruses and malware because avast! Antivirus protection is active.
http://www.avast.com
Hello,
By design, DDS "stones" like AD9852 from Analog Devices, required
separated power lines for AVDD, DVDD and VCC.
What will is simple solution for that ? I am planing to use following
approach: +5V from linear PS, then three LC filters, then three 3.3V
voltage regulators (Ex.: MC33269T) connected to each filter. Is it good
enough ?
May be its better solution for this ? Or may be that could be simplified
to join AVDD and VCC (AVDD will be connected to VCC via 100 Ohm). Thanks
in advance !
--
WBW,
V.P.
I think most people use just one regular and then use bypass caps that are
physically close to the power pins. Being really close is likely the most
important point.
What matters as much or even more is the design of the ground system. The
Vcc pins are actually easier to take care of, I think, because you can just
bypass them. but you obviously can't use a bypass can in a ground pin. On
the ground side you have to think about inductance of the traces.
On Sat, Mar 15, 2014 at 6:10 PM, d0ct0r time@patoka.org wrote:
Hello,
By design, DDS "stones" like AD9852 from Analog Devices, required
separated power lines for AVDD, DVDD and VCC.
What will is simple solution for that ? I am planing to use following
approach: +5V from linear PS, then three LC filters, then three 3.3V
voltage regulators (Ex.: MC33269T) connected to each filter. Is it good
enough ?
May be its better solution for this ? Or may be that could be simplified
to join AVDD and VCC (AVDD will be connected to VCC via 100 Ohm). Thanks in
advance !
--
WBW,
V.P.
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to
https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
--
Chris Albertson
Redondo Beach, California
By design, DDS "stones" like AD9852 from Analog Devices, required
separated power lines for AVDD, DVDD and VCC. What will is simple
solution for that ? I am planing to use following approach: +5V
from linear PS, then three LC filters, then three 3.3V voltage
regulators (Ex.: MC33269T) connected to each filter. Is it good
enough ? May be its better solution for this ? Or may be that could
be simplified to join AVDD and VCC (AVDD will be connected to VCC via 100 Ohm).
Do you have the AD evaluation board, or are you starting with the bare chip?
If you really want to know how simple you can make it, why not try it
yourself, and see what you need? You will learn a lot more that way
than by asking first every time a question occurs to you.
Follow the evaluation board plan and put a 0.1uF (100nF) monolithic
ceramic capacitor right at each power input pin of the IC itself
(something like 10 capacitors per supply).
First, use one 3.3v regulator and feed its output straight to all
three circuits, with simply a local bypass cap for each one (plus the
per-pin capacitors as noted above). Run the DDS and see how it performs.
Then, see how three separate LC filters perform (each LC fed by the
regulated 3.3v supply).
Finally, feed the unregulated supply to the "upstream" side of each
of the three LC filters, and use a separate 3.3v regulator on the
"downstream" side for each supply.
In each case, note carefully (at a lot of different output
frequencies) the general output noise level and the presence of any
spurs and birdies in the output, as well as any logic faults you find
(wrong frequency, system hangs up, bus errors, etc.).
It might be more instructive to run those steps backwards -- first,
see how it works with the most complex (and presumably best) supply,
then try the simpler circuits and see what problems crop up.
Of course, with either test protocol it is difficult to know whether
you have tried every operating state that could cause a problem, so
play with it quite a while with each setup and try to use every
function and combination.
As Chris said, you need to be very careful with your grounds. These
chips are intended to be put on boards with four or more layers. The
AD evaluation board has four layers with a common ground plane for
the analog and digital circuitry -- it is possible you could do
better with more careful attention to grounding.
Best regards,
Charles
Many thanks indeed for detailed answer ! Yes, I will using Evaluation
Board for my project.
Regards,
V.P.
On 2014-03-16 00:06, Charles Steinmetz wrote:
By design, DDS "stones" like AD9852 from Analog Devices, required
separated power lines for AVDD, DVDD and VCC. What will is simple
solution for that ? I am planing to use following approach: +5V from
linear PS, then three LC filters, then three 3.3V voltage regulators
(Ex.: MC33269T) connected to each filter. Is it good enough ? May be
its better solution for this ? Or may be that could be simplified to
join AVDD and VCC (AVDD will be connected to VCC via 100 Ohm).
Do you have the AD evaluation board, or are you starting with the bare
chip?
If you really want to know how simple you can make it, why not try it
yourself, and see what you need? You will learn a lot more that way
than by asking first every time a question occurs to you.
Follow the evaluation board plan and put a 0.1uF (100nF) monolithic
ceramic capacitor right at each power input pin of the IC itself
(something like 10 capacitors per supply).
First, use one 3.3v regulator and feed its output straight to all
three circuits, with simply a local bypass cap for each one (plus the
per-pin capacitors as noted above). Run the DDS and see how it
performs.
Then, see how three separate LC filters perform (each LC fed by the
regulated 3.3v supply).
Finally, feed the unregulated supply to the "upstream" side of each of
the three LC filters, and use a separate 3.3v regulator on the
"downstream" side for each supply.
In each case, note carefully (at a lot of different output
frequencies) the general output noise level and the presence of any
spurs and birdies in the output, as well as any logic faults you find
(wrong frequency, system hangs up, bus errors, etc.).
It might be more instructive to run those steps backwards -- first,
see how it works with the most complex (and presumably best) supply,
then try the simpler circuits and see what problems crop up.
Of course, with either test protocol it is difficult to know whether
you have tried every operating state that could cause a problem, so
play with it quite a while with each setup and try to use every
function and combination.
As Chris said, you need to be very careful with your grounds. These
chips are intended to be put on boards with four or more layers. The
AD evaluation board has four layers with a common ground plane for the
analog and digital circuitry -- it is possible you could do better
with more careful attention to grounding.
Best regards,
Charles
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to
https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
--
WBW,
V.P.
On Sat, Mar 15, 2014 at 9:21 PM, d0ct0r time@patoka.org wrote:
Many thanks indeed for detailed answer ! Yes, I will using Evaluation
Board for my project.
Then it is already done for you. They have added all the bypass caps
already on the board. Not much left for you to do. In fact you can't do
anything because all the important design work happens within millimeters
of the power and ground pins.
--
Chris Albertson
Redondo Beach, California
For inspiration you can look on this design we use for many purposes, the
design was mainly a beacon exciter but is now also used in many laboratories
in the developing of laser controlled freq. standards (1x10-18) and also as
a direct programmable freq. source with milli Herz resolution locked to a 10
MHz std.
http://rudius.net/oz2m/ngnb/dds.htm
In the bottom of the web page is diagrams of both power supply and DDS
design, the DDS is controlled by an ATMEGA 128A, all is open source.
// Michael, OZ2ELA
-----Oprindelig meddelelse-----
Fra: time-nuts-bounces@febo.com [mailto:time-nuts-bounces@febo.com] På vegne
af d0ct0r
Sendt: 16. marts 2014 05:22
Til: time-nuts@febo.com
Emne: Re: [time-nuts] Power Supply for AD9852 / AD9854
Many thanks indeed for detailed answer ! Yes, I will using Evaluation Board
for my project.
Regards,
V.P.
On 2014-03-16 00:06, Charles Steinmetz wrote:
By design, DDS "stones" like AD9852 from Analog Devices, required
separated power lines for AVDD, DVDD and VCC. What will is simple
solution for that ? I am planing to use following approach: +5V from
linear PS, then three LC filters, then three 3.3V voltage regulators
(Ex.: MC33269T) connected to each filter. Is it good enough ? May be
its better solution for this ? Or may be that could be simplified to
join AVDD and VCC (AVDD will be connected to VCC via 100 Ohm).
Do you have the AD evaluation board, or are you starting with the bare
chip?
If you really want to know how simple you can make it, why not try it
yourself, and see what you need? You will learn a lot more that way
than by asking first every time a question occurs to you.
Follow the evaluation board plan and put a 0.1uF (100nF) monolithic
ceramic capacitor right at each power input pin of the IC itself
(something like 10 capacitors per supply).
First, use one 3.3v regulator and feed its output straight to all
three circuits, with simply a local bypass cap for each one (plus the
per-pin capacitors as noted above). Run the DDS and see how it
performs.
Then, see how three separate LC filters perform (each LC fed by the
regulated 3.3v supply).
Finally, feed the unregulated supply to the "upstream" side of each of
the three LC filters, and use a separate 3.3v regulator on the
"downstream" side for each supply.
In each case, note carefully (at a lot of different output
frequencies) the general output noise level and the presence of any
spurs and birdies in the output, as well as any logic faults you find
(wrong frequency, system hangs up, bus errors, etc.).
It might be more instructive to run those steps backwards -- first,
see how it works with the most complex (and presumably best) supply,
then try the simpler circuits and see what problems crop up.
Of course, with either test protocol it is difficult to know whether
you have tried every operating state that could cause a problem, so
play with it quite a while with each setup and try to use every
function and combination.
As Chris said, you need to be very careful with your grounds. These
chips are intended to be put on boards with four or more layers. The
AD evaluation board has four layers with a common ground plane for the
analog and digital circuitry -- it is possible you could do better
with more careful attention to grounding.
Best regards,
Charles
time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to
https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
--
WBW,
V.P.
time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to
https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
Thanks ! Looks like I am on the right track.
I've attached couple of documents which could be useful. I'am going to
use two separated voltage regulators for VCC/AVDD and DVDD. And use 10
Ohm / 100Mhz ferrite board and few capacitors to "separate" VCC and
AVDD.
Regards,
V.P.
On 2014-03-16 07:34, Michael Jensen wrote:
For inspiration you can look on this design we use for many purposes,
the
design was mainly a beacon exciter but is now also used in many
laboratories
in the developing of laser controlled freq. standards (1x10-18) and
also as
a direct programmable freq. source with milli Herz resolution locked to
a 10
MHz std.
http://rudius.net/oz2m/ngnb/dds.htm
In the bottom of the web page is diagrams of both power supply and DDS
design, the DDS is controlled by an ATMEGA 128A, all is open source.
// Michael, OZ2ELA
-----Oprindelig meddelelse-----
Fra: time-nuts-bounces@febo.com [mailto:time-nuts-bounces@febo.com] På
vegne
af d0ct0r
Sendt: 16. marts 2014 05:22
Til: time-nuts@febo.com
Emne: Re: [time-nuts] Power Supply for AD9852 / AD9854
Many thanks indeed for detailed answer ! Yes, I will using Evaluation
Board
for my project.
Regards,
V.P.
On 2014-03-16 00:06, Charles Steinmetz wrote:
By design, DDS "stones" like AD9852 from Analog Devices, required
separated power lines for AVDD, DVDD and VCC. What will is simple
solution for that ? I am planing to use following approach: +5V from
linear PS, then three LC filters, then three 3.3V voltage regulators
(Ex.: MC33269T) connected to each filter. Is it good enough ? May be
its better solution for this ? Or may be that could be simplified to
join AVDD and VCC (AVDD will be connected to VCC via 100 Ohm).
Do you have the AD evaluation board, or are you starting with the bare
chip?
If you really want to know how simple you can make it, why not try it
yourself, and see what you need? You will learn a lot more that way
than by asking first every time a question occurs to you.
Follow the evaluation board plan and put a 0.1uF (100nF) monolithic
ceramic capacitor right at each power input pin of the IC itself
(something like 10 capacitors per supply).
First, use one 3.3v regulator and feed its output straight to all
three circuits, with simply a local bypass cap for each one (plus the
per-pin capacitors as noted above). Run the DDS and see how it
performs.
Then, see how three separate LC filters perform (each LC fed by the
regulated 3.3v supply).
Finally, feed the unregulated supply to the "upstream" side of each of
the three LC filters, and use a separate 3.3v regulator on the
"downstream" side for each supply.
In each case, note carefully (at a lot of different output
frequencies) the general output noise level and the presence of any
spurs and birdies in the output, as well as any logic faults you find
(wrong frequency, system hangs up, bus errors, etc.).
It might be more instructive to run those steps backwards -- first,
see how it works with the most complex (and presumably best) supply,
then try the simpler circuits and see what problems crop up.
Of course, with either test protocol it is difficult to know whether
you have tried every operating state that could cause a problem, so
play with it quite a while with each setup and try to use every
function and combination.
As Chris said, you need to be very careful with your grounds. These
chips are intended to be put on boards with four or more layers. The
AD evaluation board has four layers with a common ground plane for the
analog and digital circuitry -- it is possible you could do better
with more careful attention to grounding.
Best regards,
Charles
time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to
https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
--
WBW,
V.P.
time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to
https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
--
WBW,
V.P.
I do not know if this is of interest or would be applicable. Wenzel uses their Finesse Voltage Regulator in many products which I may be better described as active noise cancelling regulator.
From: albertson.chris@gmail.com
Date: Sat, 15 Mar 2014 22:36:23 -0700
To: time@patoka.org; time-nuts@febo.com
Subject: Re: [time-nuts] Power Supply for AD9852 / AD9854
On Sat, Mar 15, 2014 at 9:21 PM, d0ct0r time@patoka.org wrote:
Many thanks indeed for detailed answer ! Yes, I will using Evaluation
Board for my project.
Then it is already done for you. They have added all the bypass caps
already on the board. Not much left for you to do. In fact you can't do
anything because all the important design work happens within millimeters
of the power and ground pins.
--
Chris Albertson
Redondo Beach, California
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
Sorry, I forgot to add the link:
http://www.wenzel.com/documents/finesse.html
Thomas Knox
From: actast@hotmail.com
To: time-nuts@febo.com
Date: Sun, 16 Mar 2014 09:46:04 -0600
Subject: Re: [time-nuts] Power Supply for AD9852 / AD9854
I do not know if this is of interest or would be applicable. Wenzel uses their Finesse Voltage Regulator in many products which I may be better described as active noise cancelling regulator.
From: albertson.chris@gmail.com
Date: Sat, 15 Mar 2014 22:36:23 -0700
To: time@patoka.org; time-nuts@febo.com
Subject: Re: [time-nuts] Power Supply for AD9852 / AD9854
On Sat, Mar 15, 2014 at 9:21 PM, d0ct0r time@patoka.org wrote:
Many thanks indeed for detailed answer ! Yes, I will using Evaluation
Board for my project.
Then it is already done for you. They have added all the bypass caps
already on the board. Not much left for you to do. In fact you can't do
anything because all the important design work happens within millimeters
of the power and ground pins.
--
Chris Albertson
Redondo Beach, California
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
On 3/16/14 8:13 AM, d0ct0r wrote:
Thanks ! Looks like I am on the right track.
I've attached couple of documents which could be useful. I'am going to
use two separated voltage regulators for VCC/AVDD and DVDD. And use 10
Ohm / 100Mhz ferrite board and few capacitors to "separate" VCC and AVDD.
those parts dissipate a fair amount of heat, and they're not very big.
If you turn on everything in the 9854 AND run it at 300 MHz clock, it
draws about 1.2 Amps (@ 3.3V) which is about 4 Watts.. that's a lot of
power to get out of the part and keep Tj reasonable. Board layout to get
the heat out is very important. If they get too hot, they start to act
flaky. You get extra spurs and more importantly, they don't respond to
the programming properly (e.g. you send the serial stream to program
frequency X, and instead it programs some different frequency).
"The heat sink of the AD9854ASVZ 80-lead TQFP package must
be soldered to the PCB. "
"Adequate dissipation of heat from the AD9854 relies on all
power and ground pins of the device being soldered directly to
a copper plane on a PCB. In addition, the thermally enhanced
package of the AD9854ASVZ has an exposed paddle on the
bottom of the package that must be soldered to a large copper
plane, which, for convenience, can be the ground plane."
I would assume that using two voltage regulators will spread the load.
For the AD9851 I'am planning to put external radiator glued on top of
it.
Regards,
V.P.
those parts dissipate a fair amount of heat, and they're not very big.
If you turn on everything in the 9854 AND run it at 300 MHz clock, it
draws about 1.2 Amps (@ 3.3V) which is about 4 Watts.. that's a lot of
power to get out of the part and keep Tj reasonable. Board layout to
get the heat out is very important. If they get too hot, they start
to act flaky. You get extra spurs and more importantly, they don't
respond to the programming properly (e.g. you send the serial stream
to program frequency X, and instead it programs some different
frequency).
"The heat sink of the AD9854ASVZ 80-lead TQFP package must
be soldered to the PCB. "
"Adequate dissipation of heat from the AD9854 relies on all
power and ground pins of the device being soldered directly to
a copper plane on a PCB. In addition, the thermally enhanced
package of the AD9854ASVZ has an exposed paddle on the
bottom of the package that must be soldered to a large copper
plane, which, for convenience, can be the ground plane."
--
WBW,
V.P.
My versions of a DDS using two AD9910 in Quadrature
http://members.wideband.net.au/gzimmer/QuadDDS/default.html
regards ....... Zm
On 3/16/14 9:34 AM, d0ct0r wrote:
I would assume that using two voltage regulators will spread the load.
For the AD9851 I'am planning to put external radiator glued on top of it.
It's not the power dissipation of the regulators that's the concern,
it's the dissipation of the 9854. A heatsink on top doesn't do much for
it, since the thermal path is out through the bottom and/or the leads.
Of course, if your regulators are sharing the thermal path, then
dissipation in the regulators becomes a concern too.
Read the data sheet and the ap note for details.
The eval board works OK most of the time. I've encountered flaky
behavior but that could have been from other causes.
The 9854 is the part that was used in the Flex-Radio SDR1000, but most
of the options were powered off, so the dissipation was in the <1 watt
range. That particular board would overheat in an enclosure if you
didn't have a fan blowing on it.
Hi
If you use multiple regulators for the same supply and they don’t come up at the same time, odd things can happen. On some chips those odd things include smoke. In most cases where it fails, the more common effect is the internal reset does not work properly and you can’t talk to the chip.
You really need a multi layer board to heat spread these chips, you also need to reflow solder them to get the bottom pad properly connected to the via’s under the chip. Unless it’s already on a board, this is not a simple chip to use in a home environment.
Bob
On Mar 16, 2014, at 12:34 PM, d0ct0r time@patoka.org wrote:
I would assume that using two voltage regulators will spread the load. For the AD9851 I'am planning to put external radiator glued on top of it.
Regards,
V.P.
those parts dissipate a fair amount of heat, and they're not very big.
If you turn on everything in the 9854 AND run it at 300 MHz clock, it
draws about 1.2 Amps (@ 3.3V) which is about 4 Watts.. that's a lot of
power to get out of the part and keep Tj reasonable. Board layout to
get the heat out is very important. If they get too hot, they start
to act flaky. You get extra spurs and more importantly, they don't
respond to the programming properly (e.g. you send the serial stream
to program frequency X, and instead it programs some different
frequency).
"The heat sink of the AD9854ASVZ 80-lead TQFP package must
be soldered to the PCB. "
"Adequate dissipation of heat from the AD9854 relies on all
power and ground pins of the device being soldered directly to
a copper plane on a PCB. In addition, the thermally enhanced
package of the AD9854ASVZ has an exposed paddle on the
bottom of the package that must be soldered to a large copper
plane, which, for convenience, can be the ground plane."
--
WBW,
V.P.
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
Unless it’s already on a board, this is not a simple chip to use in a home environment.
Nevertheless, some of us do manage.
But it's true, the AD9852/AD9854 does run very hot.
It's worth mentioning that the AD9910/AD9912 family runs much cooler.
Mine aren't even warm to the touch. This of course is due to the power
hungry parts of the chip running on 1.8V instead of 3.3V
......... Zim
I mentioned the need to be careful with grounding in mixed-signal
circuits. This Analog Devices tutorial is a useful introduction to
the subject, for those interested:
Grounding Data Converters and Solving the Mystery of "AGND" and "DGND"
http://www.analog.com/static/imported-files/tutorials/MT-031.pdf
Best regards,
Charles