Javier Herrero wrote:

hysteresis is in the 100mV minimum range, and max peak amplitude is in
the 0.9 to 1 Volt range (they'll have a bias point a bit over a volt,
and a lot of them do not do well at all if you swing close to the supply
rail)

Maybe with external clamps and over drive it.

El 09/12/2010 15:21, jimlux escribió:

Yes, I was thinking in that way. But surely they are better solutions :)

Regards,

Javier

--

Javier Herrero                            EMAIL: jherrero@hvsistemas.com
Chief Technology Officer
HV Sistemas S.L.                          PHONE:        +34 949 336 806
Los Charcones, 17                        FAX:          +34 949 336 792
19170 El Casar - Guadalajara - Spain      WEB: http://www.hvsistemas.com

Javier Herrero wrote:

hence my question to the list..

I'm going to gather all the responses and summarize them for the list
later today.

jimlux wrote:

Since noise modulation (power supply and device noise) of device
parameters (eg collector base capacitance) can be a significant source
of phase noise adding some emitter degeneration in a long tailed pair
and shunting the collector load resistors with inductors (eg a
transformer winding) should be an effective way of reducing such phase
noise. A capacitor shunting the collector load can also be effective in
reducing the circuit bandwidth closer to the optimum and desensitising
the circuit bandwidth to device parameter variations. However avoiding
high Q parasitic resonances with the output inductors (or transformer)
will be necessary.

Bruce

There are some nice residual plots for AC and CMOS chips at
http://www.xs4all.nl/~martein/pa3ake/hmode/dds_ad9910_pmnoise.html .  Seems
like the AD9515 family in PECL mode is about as good as anything is likely
to get at VHF.

However, why not use the sine wave directly, converted to differential with
a transformer and clipped by back-to-back Schottkys?  At VHF clock
frequencies any active sine-to-square conversion circuit I'm aware of will
contribute more jitter than the ADC's own tJ spec.  (Put another way, if I'm
a semiconductor house designing a high-end ADC or DAC, I am probably going
to put all the secret sauce I have into the on-chip clock conditioning,
leaving little or no room for improvement outside the chip.)

The eval boards from the various ADC manufacturers bear this out.  No one
puts anything but a 50-ohm SMA jack, transformer and Schottkys on their
clock inputs.

-- john, KE5FX

Hi

...and sometimes they leave the Schottkys out.

The original request was not a really low jitter application. I think Jim
can get away with an active circuit.

Bob

-----Original Message-----
From: time-nuts-bounces@febo.com [mailto:time-nuts-bounces@febo.com] On
Behalf Of John Miles
Sent: Thursday, December 09, 2010 4:00 PM
To: Discussion of precise time and frequency measurement
Subject: Re: [time-nuts] reference oscillator input circuit

There are some nice residual plots for AC and CMOS chips at
http://www.xs4all.nl/~martein/pa3ake/hmode/dds_ad9910_pmnoise.html .  Seems
like the AD9515 family in PECL mode is about as good as anything is likely
to get at VHF.

However, why not use the sine wave directly, converted to differential with
a transformer and clipped by back-to-back Schottkys?  At VHF clock
frequencies any active sine-to-square conversion circuit I'm aware of will
contribute more jitter than the ADC's own tJ spec.  (Put another way, if I'm
a semiconductor house designing a high-end ADC or DAC, I am probably going
to put all the secret sauce I have into the on-chip clock conditioning,
leaving little or no room for improvement outside the chip.)

The eval boards from the various ADC manufacturers bear this out.  No one
puts anything but a 50-ohm SMA jack, transformer and Schottkys on their
clock inputs.

-- john, KE5FX

time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to
https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.