Frequency subtraction with D-flip flops
I still can't tell if my email is messed up. Last time the second
attempt went right through. I'm trying again now. Please excuse if
the redundant original shows up too.
Original message:
I am revisiting that tracking generator reference I brought up here a
while back, and trying to get my head around how a DFF can take the
difference between two frequencies. I have studied and thought about
the various topologies and conditions, and searched online for good
explanations, but haven't found anything concise that applies to this
simple case. During the last discussion on this matter, I learned
that another DFF should follow the first, and be clocked the same, in
order to reduce effects of metastability. For the actual application,
I believe there are limits to the differencing process, so I'd like
to check here to see if my thinking is right.
First, let's call fd the frequency of the D-input, and fc the clock,
which produce a signal fo at the Q output of the first DFF.
-
It seems to me that whenever fd and fc are within a factor of two
of each other, either one can be viewed as sampling the other below
the Nyquist rate, so an alias signal fo, the difference frequency, is
produced. It doesn't matter which input frequency is higher. -
It seems to me that whenever fc is much higher than fd (fc>>fd),
then it's clearly sampling above Nyquist frequency, so no aliasing
occurs - just a delayed (by a fraction of a cycle of fc) version of
fd shows up at the Q output, and fo=fd. If so, then this should be
true all the way down to fc>2*fd. -
It seems to me that whenever fd is much higher than fc (fd>>fc),
then it's clearly undersampling, so aliasing will occur, producing
fo=fd-nfc, where n is the highest integer that allows fd>nfc. If
so, then this should be true all the way down to fd>2fc. For
example, if fc is 200 kHz, and fd is 15.8833333 MHz, then n=79, and
fo=83.3333 kHz. 790.2=15.8 MHz, so 15.883333-15.8=.08333 MHz. If
fc=5 MHz, then n=3, and fo=883.3333 kHz. If fc=4 MHz, then n=3, and
fo=3.883333 MHz.
Now onto the second DFF, which reduces the metastability effects of
the first. Let's say that normally the Q output of the first goes to
the D input of the second, the clocks of both are the same fc, and
the Q output of the second is the "cleaned up" version of fo, delayed
by a fraction of a cycle of fc.
-
It seems to me that whenever fd is much higher than fc (fd>>fc),
that fd could be used instead to trigger the second DFF, which would
reduce the metastability of the first DFF somewhat, and also
synchronize the output signal closer to the edges of fd - but with
some metastability from that too. -
It seems to me that the fastest possible logic family should be
used for minimum metastability, even if slower ones can clock easily
at fc and fd. So, I'd prefer 74AC-type parts over HC, even at 15 MHz.
So, do I get it, or am I missing something? Please be nice.
Ed
On Tue, Jun 25, 2013 at 4:36 AM, ed breya eb@telight.com wrote:
- It seems to me that whenever fd is much higher than fc (fd>>fc), that
fd could be used instead to trigger the second DFF, which would reduce the
metastability of the first DFF somewhat, and also synchronize the output
signal closer to the edges of fd - but with some metastability from that
too.
Clocking the two FFs of a synchronizer with different clock signals will
not work against metastability. When the edges of fd and fc are very close
in time, there is a slight chance that the output of the first FF will be
in a metastable state for some time. By clocking the second FF with fc you
allow for a full (guaranteed) period of fc for that output to stabilize to
a solid '0' or '1'. If you clock the two FFs with two different clock
signals you don't have that guarantee. There should be a big gain to be had
somewhere else to do something like that, but I can't see it. I must say
all my experience is with fc very close to fd in frequency, so maybe I am
missing something about the fd>>fc case.
Cheers,
Javier
Javier Serrano wrote:
On Tue, Jun 25, 2013 at 4:36 AM, ed breyaeb@telight.com wrote:
- It seems to me that whenever fd is much higher than fc (fd>>fc), that
fd could be used instead to trigger the second DFF, which would reduce the
metastability of the first DFF somewhat, and also synchronize the output
signal closer to the edges of fd - but with some metastability from that
too.
Clocking the two FFs of a synchronizer with different clock signals will
not work against metastability. When the edges of fd and fc are very close
in time, there is a slight chance that the output of the first FF will be
in a metastable state for some time. By clocking the second FF with fc you
allow for a full (guaranteed) period of fc for that output to stabilize to
a solid '0' or '1'. If you clock the two FFs with two different clock
signals you don't have that guarantee. There should be a big gain to be had
somewhere else to do something like that, but I can't see it. I must say
all my experience is with fc very close to fd in frequency, so maybe I am
missing something about the fd>>fc case.
Cheers,
Javier
US patent 6441601 describes using a D flipflop as a phase detector when
fc>fd.
Fd ~ 13.4Mhz, Fc ~ 10.23MHz
In this case the samples are permuted to achieve the right order of
phase differences.
I have clocked a 74HC164 with a 5.000055MHz fc whilst the D input is
driven at 10.000 MHz to produce a 110 Hz " beat note".
Bruce
Thanks, Bruce, for that wonderful phase meter patent reference. Very interesting.
BTW, if any of you are wondering why the patent mentions comparing 10.23 MHz (GPS) with a "very accurate" 13.4 MHz, the following paper explains that our favorite cesium frequency 9192.631770 MHz / 686 = 13.400... MHz:
http://www.pttimeeting.org/archivemeetings/1992papers/Vol%2024_20.pdf
/tvb