Empathy List Archives

TF

Torres Figueroa, Luis Angel

Wed, Aug 16, 2017 2:15 PM

Hi folks,

Has someone of you loaded the whole usrp_x310_fpga_RFNOC_HG design into Vivado 2015.4 and created the FPGA image using its graphical Interface? I am still unable to do so.

I want to create a standard FPGA image using Vivado GUI.

I have first run the command “make X310_RFNOC_HG GUI=1”, saved the whole RTS design and reopened it as project mode, and then tried to create the bitstream from the GUI itself but it doesn’t work.

I have also tried adding the x300.v file, the constraints and all its dependent files into the design, and then done the synthesis, implementation and generated the bitstream, but when I loaded it onto the USRP I can’t recognize any block using the command uhd_usrp_probe. This is the error I get:

[ERROR] [UHD] Exception caught in safe-call.
in virtual ctrl_iface_impl::~ctrl_iface_impl()
at ~/uhd/host/lib/rfnoc/ctrl_iface.cpp:76
this->peek32(0); -> EnvironmentError: IOError: Block ctrl (CE_04_Port_70) no response packet - AssertionError: bool(buff)
in uint64_t ctrl_iface_impl::wait_for_ack(bool)
at ~/uhd/host/lib/rfnoc/ctrl_iface.cpp:197

Best,
Luis A. Torres

Hi folks, Has someone of you loaded the whole usrp_x310_fpga_RFNOC_HG design into Vivado 2015.4 and created the FPGA image using its graphical Interface? I am still unable to do so. I want to create a standard FPGA image using Vivado GUI. I have first run the command “make X310_RFNOC_HG GUI=1”, saved the whole RTS design and reopened it as project mode, and then tried to create the bitstream from the GUI itself but it doesn’t work. I have also tried adding the x300.v file, the constraints and all its dependent files into the design, and then done the synthesis, implementation and generated the bitstream, but when I loaded it onto the USRP I can’t recognize any block using the command uhd_usrp_probe. This is the error I get: [ERROR] [UHD] Exception caught in safe-call. in virtual ctrl_iface_impl::~ctrl_iface_impl() at ~/uhd/host/lib/rfnoc/ctrl_iface.cpp:76 this->peek32(0); -> EnvironmentError: IOError: Block ctrl (CE_04_Port_70) no response packet - AssertionError: bool(buff) in uint64_t ctrl_iface_impl::wait_for_ack(bool) at ~/uhd/host/lib/rfnoc/ctrl_iface.cpp:197 Best, Luis A. Torres

JM

Jason Matusiak

Wed, Aug 16, 2017 3:08 PM

I've done it many times. When you open it and you do a save-as of the
project, make sure that you don't check the option box to copy the files
over, you want to leave them in their current location.

On 08/16/2017 10:15 AM, Torres Figueroa, Luis Angel via USRP-users wrote:

Hi folks,

Has someone of you loaded the whole usrp_x310_fpga_RFNOC_HG design
into Vivado 2015.4 and created the FPGA image using its graphical
Interface? I am still unable to do so.

I want to create a standard FPGA image using Vivado GUI.

I have first run the command /“//make X310_RFNOC_HG GUI=1”/, saved the
whole RTS design and reopened it as project mode, and then tried to
create the bitstream from the GUI itself but it doesn’t work.

I have also tried adding the x300.v file, the constraints and all its
dependent files into the design, and then done the synthesis,
implementation and generated the bitstream, but when I loaded it onto
the USRP I can’t recognize any block using the command uhd_usrp_probe.
This is the error I get:

[ERROR] [UHD] Exception caught in safe-call.

in virtual ctrl_iface_impl::~ctrl_iface_impl()

at ~/uhd/host/lib/rfnoc/ctrl_iface.cpp:76

this->peek32(0); -> EnvironmentError: IOError: Block ctrl
(CE_04_Port_70) no response packet - AssertionError: bool(buff)

in uint64_t ctrl_iface_impl::wait_for_ack(bool)

at ~/uhd/host/lib/rfnoc/ctrl_iface.cpp:197

Best,

Luis A. Torres

USRP-users mailing list
USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com

I've done it many times. When you open it and you do a save-as of the project, make sure that you don't check the option box to copy the files over, you want to leave them in their current location. On 08/16/2017 10:15 AM, Torres Figueroa, Luis Angel via USRP-users wrote: > > Hi folks, > > Has someone of you loaded the whole usrp_x310_fpga_RFNOC_HG design > into Vivado 2015.4 and created the FPGA image using its graphical > Interface? I am still unable to do so. > > I want to create a standard FPGA image using Vivado GUI. > > I have first run the command /“//make X310_RFNOC_HG GUI=1”/, saved the > whole RTS design and reopened it as project mode, and then tried to > create the bitstream from the GUI itself but it doesn’t work. > > I have also tried adding the x300.v file, the constraints and all its > dependent files into the design, and then done the synthesis, > implementation and generated the bitstream, but when I loaded it onto > the USRP I can’t recognize any block using the command uhd_usrp_probe. > This is the error I get: > > [ERROR] [UHD] Exception caught in safe-call. > > in virtual ctrl_iface_impl::~ctrl_iface_impl() > > at ~/uhd/host/lib/rfnoc/ctrl_iface.cpp:76 > > this->peek32(0); -> EnvironmentError: IOError: Block ctrl > (CE_04_Port_70) no response packet - AssertionError: bool(buff) > > in uint64_t ctrl_iface_impl::wait_for_ack(bool) > > at ~/uhd/host/lib/rfnoc/ctrl_iface.cpp:197 > > Best, > > Luis A. Torres > > > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com

TF

Torres Figueroa, Luis Angel

Fri, Aug 18, 2017 1:26 PM

Hi Jason,

It worked. I downloaded the source files from rfnoc-devel branch in the repository again and build it without choosing the option you mentioned.

I have still some critical warnings, but the image has been correctly generated and I could use it in the URSP. Also, all the timing constraints were now met. Thanks for the advice!

ImplementationDesign Initialization
[Designutils 20-1280] Could not find module 'fifo_4k_2clk'. The XDC file /home/rfnoc-devel/source/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk.xdc will not be read for any cell of this module.
[Designutils 20-1280] Could not find module 'axi_hb31'. The XDC file /home/rfnoc-devel/source/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb31/fir_compiler_v7_2_5/constraints/fir_compiler_v7_2.xdc will not be read for any cell of this module.
[Designutils 20-1280] Could not find module 'fifo_4k_2clk'. The XDC file /home/rfnoc-devel/source/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk_clocks.xdc will not be read for any cell of this module.
[Common 17-55] 'set_property' expects at least one object. ["/home/rfnoc-devel/source/uhd/fpga-src/usrp3/top/x300/timing.xdc":293]
[Common 17-55] 'set_property' expects at least one object. ["/home/rfnoc-devel/source/uhd/fpga-src/usrp3/top/x300/timing.xdc":294]
[Common 17-55] 'set_property' expects at least one object. ["/home/rfnoc-devel/source/uhd/fpga-src/usrp3/top/x300/timing.xdc":295]

Best,
Luis

Von: Jason Matusiak jason@gardettoengineering.com
Datum: Mittwoch, 16. August 2017 um 17:09
An: "Torres Figueroa, Luis Angel" luis.torres.figueroa@rwth-aachen.de, "usrp-users@lists.ettus.com" usrp-users@lists.ettus.com
Betreff: Re: [USRP-users] Building FPGA image

I've done it many times. When you open it and you do a save-as of the project, make sure that you don't check the option box to copy the files over, you want to leave them in their current location.

On 08/16/2017 10:15 AM, Torres Figueroa, Luis Angel via USRP-users wrote:
Hi folks,

Has someone of you loaded the whole usrp_x310_fpga_RFNOC_HG design into Vivado 2015.4 and created the FPGA image using its graphical Interface? I am still unable to do so.

I want to create a standard FPGA image using Vivado GUI.

I have first run the command “make X310_RFNOC_HG GUI=1”, saved the whole RTS design and reopened it as project mode, and then tried to create the bitstream from the GUI itself but it doesn’t work.

I have also tried adding the x300.v file, the constraints and all its dependent files into the design, and then done the synthesis, implementation and generated the bitstream, but when I loaded it onto the USRP I can’t recognize any block using the command uhd_usrp_probe. This is the error I get:

[ERROR] [UHD] Exception caught in safe-call.
in virtual ctrl_iface_impl::~ctrl_iface_impl()
at ~/uhd/host/lib/rfnoc/ctrl_iface.cpp:76
this->peek32(0); -> EnvironmentError: IOError: Block ctrl (CE_04_Port_70) no response packet - AssertionError: bool(buff)
in uint64_t ctrl_iface_impl::wait_for_ack(bool)
at ~/uhd/host/lib/rfnoc/ctrl_iface.cpp:197

Best,
Luis A. Torres

USRP-users mailing list

USRP-users@lists.ettus.com mailto:USRP-users@lists.ettus.com

http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com

Hi Jason, It worked. I downloaded the source files from rfnoc-devel branch in the repository again and build it without choosing the option you mentioned. I have still some critical warnings, but the image has been correctly generated and I could use it in the URSP. Also, all the timing constraints were now met. Thanks for the advice! ImplementationDesign Initialization [Designutils 20-1280] Could not find module 'fifo_4k_2clk'. The XDC file /home/rfnoc-devel/source/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk.xdc will not be read for any cell of this module. [Designutils 20-1280] Could not find module 'axi_hb31'. The XDC file /home/rfnoc-devel/source/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb31/fir_compiler_v7_2_5/constraints/fir_compiler_v7_2.xdc will not be read for any cell of this module. [Designutils 20-1280] Could not find module 'fifo_4k_2clk'. The XDC file /home/rfnoc-devel/source/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk_clocks.xdc will not be read for any cell of this module. [Common 17-55] 'set_property' expects at least one object. ["/home/rfnoc-devel/source/uhd/fpga-src/usrp3/top/x300/timing.xdc":293] [Common 17-55] 'set_property' expects at least one object. ["/home/rfnoc-devel/source/uhd/fpga-src/usrp3/top/x300/timing.xdc":294] [Common 17-55] 'set_property' expects at least one object. ["/home/rfnoc-devel/source/uhd/fpga-src/usrp3/top/x300/timing.xdc":295] Best, Luis Von: Jason Matusiak <jason@gardettoengineering.com> Datum: Mittwoch, 16. August 2017 um 17:09 An: "Torres Figueroa, Luis Angel" <luis.torres.figueroa@rwth-aachen.de>, "usrp-users@lists.ettus.com" <usrp-users@lists.ettus.com> Betreff: Re: [USRP-users] Building FPGA image I've done it many times. When you open it and you do a save-as of the project, make sure that you don't check the option box to copy the files over, you want to leave them in their current location. On 08/16/2017 10:15 AM, Torres Figueroa, Luis Angel via USRP-users wrote: Hi folks, Has someone of you loaded the whole usrp_x310_fpga_RFNOC_HG design into Vivado 2015.4 and created the FPGA image using its graphical Interface? I am still unable to do so. I want to create a standard FPGA image using Vivado GUI. I have first run the command “make X310_RFNOC_HG GUI=1”, saved the whole RTS design and reopened it as project mode, and then tried to create the bitstream from the GUI itself but it doesn’t work. I have also tried adding the x300.v file, the constraints and all its dependent files into the design, and then done the synthesis, implementation and generated the bitstream, but when I loaded it onto the USRP I can’t recognize any block using the command uhd_usrp_probe. This is the error I get: [ERROR] [UHD] Exception caught in safe-call. in virtual ctrl_iface_impl::~ctrl_iface_impl() at ~/uhd/host/lib/rfnoc/ctrl_iface.cpp:76 this->peek32(0); -> EnvironmentError: IOError: Block ctrl (CE_04_Port_70) no response packet - AssertionError: bool(buff) in uint64_t ctrl_iface_impl::wait_for_ack(bool) at ~/uhd/host/lib/rfnoc/ctrl_iface.cpp:197 Best, Luis A. Torres _______________________________________________ USRP-users mailing list USRP-users@lists.ettus.com<mailto:USRP-users@lists.ettus.com> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com

JM

Jason Matusiak

Fri, Aug 18, 2017 4:42 PM

I'm glad you got it working. There are a lot of critical warnings and
things of that ilk that scroll by, but as long as you don't get any
errors and your project meets timing, I wouldn't worry too much about them.

Happy FPGAing.

On 08/18/2017 09:26 AM, Torres Figueroa, Luis Angel wrote:

Hi Jason,

It worked. I downloaded the source files from rfnoc-devel branch in
the repository again and build it without choosing the option you
mentioned.

I have still some critical warnings, but the image has been correctly
generated and I could use it in the URSP. Also, all the timing
constraints were now met. Thanks for the advice!

ImplementationDesign Initialization

[Designutils 20-1280] Could not find module 'fifo_4k_2clk'. The XDC
file
/home/rfnoc-devel/source/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk.xdc
will not be read for any cell of this module.

[Designutils 20-1280] Could not find module 'axi_hb31'. The XDC file
/home/rfnoc-devel/source/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb31/fir_compiler_v7_2_5/constraints/fir_compiler_v7_2.xdc
will not be read for any cell of this module.

[Designutils 20-1280] Could not find module 'fifo_4k_2clk'. The XDC
file
/home/rfnoc-devel/source/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk_clocks.xdc
will not be read for any cell of this module.

[Common 17-55] 'set_property' expects at least one object.
["/home/rfnoc-devel/source/uhd/fpga-src/usrp3/top/x300/timing.xdc":293]

[Common 17-55] 'set_property' expects at least one object.
["/home/rfnoc-devel/source/uhd/fpga-src/usrp3/top/x300/timing.xdc":294]

[Common 17-55] 'set_property' expects at least one object.
["/home/rfnoc-devel/source/uhd/fpga-src/usrp3/top/x300/timing.xdc":295]

Best,

Luis

*Von: *Jason Matusiak jason@gardettoengineering.com
*Datum: *Mittwoch, 16. August 2017 um 17:09
*An: *"Torres Figueroa, Luis Angel"
luis.torres.figueroa@rwth-aachen.de, "usrp-users@lists.ettus.com"
usrp-users@lists.ettus.com
*Betreff: *Re: [USRP-users] Building FPGA image

I've done it many times. When you open it and you do a save-as of the
project, make sure that you don't check the option box to copy the
files over, you want to leave them in their current location.

On 08/16/2017 10:15 AM, Torres Figueroa, Luis Angel via USRP-users wrote:

 Hi folks,

 Has someone of you loaded the whole usrp_x310_fpga_RFNOC_HG design
 into Vivado 2015.4 and created the FPGA image using its graphical
 Interface? I am still unable to do so.

 I want to create a standard FPGA image using Vivado GUI.

 I have first run the command /“make X310_RFNOC_HG GUI=1”/, saved
 the whole RTS design and reopened it as project mode, and then
 tried to create the bitstream from the GUI itself but it doesn’t work.

 I have also tried adding the x300.v file, the constraints and all
 its dependent files into the design, and then done the synthesis,
 implementation and generated the bitstream, but when I loaded it
 onto the USRP I can’t recognize any block using the command
 uhd_usrp_probe. This is the error I get:

 [ERROR] [UHD] Exception caught in safe-call.

   in virtual ctrl_iface_impl::~ctrl_iface_impl()

   at ~/uhd/host/lib/rfnoc/ctrl_iface.cpp:76

 this->peek32(0); -> EnvironmentError: IOError: Block ctrl
 (CE_04_Port_70) no response packet - AssertionError: bool(buff)

   in uint64_t ctrl_iface_impl::wait_for_ack(bool)

   at ~/uhd/host/lib/rfnoc/ctrl_iface.cpp:197

 Best,

 Luis A. Torres




 _______________________________________________

 USRP-users mailing list

 USRP-users@lists.ettus.com <mailto:USRP-users@lists.ettus.com>

 http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com

I'm glad you got it working. There are a lot of critical warnings and things of that ilk that scroll by, but as long as you don't get any errors and your project meets timing, I wouldn't worry too much about them. Happy FPGAing. On 08/18/2017 09:26 AM, Torres Figueroa, Luis Angel wrote: > > Hi Jason, > > It worked. I downloaded the source files from rfnoc-devel branch in > the repository again and build it without choosing the option you > mentioned. > > I have still some critical warnings, but the image has been correctly > generated and I could use it in the URSP. Also, all the timing > constraints were now met. Thanks for the advice! > > ImplementationDesign Initialization > > [Designutils 20-1280] Could not find module 'fifo_4k_2clk'. The XDC > file > /home/rfnoc-devel/source/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk.xdc > will not be read for any cell of this module. > > [Designutils 20-1280] Could not find module 'axi_hb31'. The XDC file > /home/rfnoc-devel/source/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb31/fir_compiler_v7_2_5/constraints/fir_compiler_v7_2.xdc > will not be read for any cell of this module. > > [Designutils 20-1280] Could not find module 'fifo_4k_2clk'. The XDC > file > /home/rfnoc-devel/source/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk_clocks.xdc > will not be read for any cell of this module. > > [Common 17-55] 'set_property' expects at least one object. > ["/home/rfnoc-devel/source/uhd/fpga-src/usrp3/top/x300/timing.xdc":293] > > [Common 17-55] 'set_property' expects at least one object. > ["/home/rfnoc-devel/source/uhd/fpga-src/usrp3/top/x300/timing.xdc":294] > > [Common 17-55] 'set_property' expects at least one object. > ["/home/rfnoc-devel/source/uhd/fpga-src/usrp3/top/x300/timing.xdc":295] > > Best, > > Luis > > *Von: *Jason Matusiak <jason@gardettoengineering.com> > *Datum: *Mittwoch, 16. August 2017 um 17:09 > *An: *"Torres Figueroa, Luis Angel" > <luis.torres.figueroa@rwth-aachen.de>, "usrp-users@lists.ettus.com" > <usrp-users@lists.ettus.com> > *Betreff: *Re: [USRP-users] Building FPGA image > > I've done it many times. When you open it and you do a save-as of the > project, make sure that you don't check the option box to copy the > files over, you want to leave them in their current location. > > On 08/16/2017 10:15 AM, Torres Figueroa, Luis Angel via USRP-users wrote: > > Hi folks, > > Has someone of you loaded the whole usrp_x310_fpga_RFNOC_HG design > into Vivado 2015.4 and created the FPGA image using its graphical > Interface? I am still unable to do so. > > I want to create a standard FPGA image using Vivado GUI. > > I have first run the command /“make X310_RFNOC_HG GUI=1”/, saved > the whole RTS design and reopened it as project mode, and then > tried to create the bitstream from the GUI itself but it doesn’t work. > > I have also tried adding the x300.v file, the constraints and all > its dependent files into the design, and then done the synthesis, > implementation and generated the bitstream, but when I loaded it > onto the USRP I can’t recognize any block using the command > uhd_usrp_probe. This is the error I get: > > [ERROR] [UHD] Exception caught in safe-call. > > in virtual ctrl_iface_impl::~ctrl_iface_impl() > > at ~/uhd/host/lib/rfnoc/ctrl_iface.cpp:76 > > this->peek32(0); -> EnvironmentError: IOError: Block ctrl > (CE_04_Port_70) no response packet - AssertionError: bool(buff) > > in uint64_t ctrl_iface_impl::wait_for_ack(bool) > > at ~/uhd/host/lib/rfnoc/ctrl_iface.cpp:197 > > Best, > > Luis A. Torres > > > > > _______________________________________________ > > USRP-users mailing list > > USRP-users@lists.ettus.com <mailto:USRP-users@lists.ettus.com> > > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > > >