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AT

Anders Time

Fri, Jan 25, 2008 12:23 PM

What is the best way to generate a very stable 10.001MHz(low E-13 or
-110dBc/1Hz) to be to do high resolution heterodyne(Allan deviation)
measurements?
Using DDS?
Using PTS 500 or 250 synth and divide? Using HP 8662A and divide?
Some smart pll circuit by locking the 1000Hz to the reference in some way?
Thanks
Anders

What is the best way to generate a very stable 10.001MHz(low E-13 or -110dBc/1Hz) to be to do high resolution heterodyne(Allan deviation) measurements? Using DDS? Using PTS 500 or 250 synth and divide? Using HP 8662A and divide? Some smart pll circuit by locking the 1000Hz to the reference in some way? Thanks Anders

JA

John Ackermann N8UR

Fri, Jan 25, 2008 12:56 PM

Anders Time said the following on 01/25/2008 07:23 AM:

What is the best way to generate a very stable 10.001MHz(low E-13 or
-110dBc/1Hz) to be to do high resolution heterodyne(Allan deviation)
measurements?
Using DDS?
Using PTS 500 or 250 synth and divide? Using HP 8662A and divide?
Some smart pll circuit by locking the 1000Hz to the reference in some way?
Thanks
Anders

Rick Karlquist has published a design for a very low noise synthesizer
designed for just this application. Unfortunately, I don't have a link
to that handy, but it's on his website.

I just took a look at some measurements I did on a PTS-250-SX51 (special
version with low noise output to 25 MHz via an internal divider) and it
looks like it would barely meet your requirements -- around 2x10e-13 at
1 second, and about -115 dBc/Hz at 1 Hz offset:

http://www.febo.com/pages/pts_synth/images/pts-250-sx51-adev.png
http://www.febo.com/pages/pts_synth/images/pts-250-sx51-spectrum.png

However, that was at 10.000... MHz; the performance, particularly with
respect to spurs, changes as the decimal dividers kick in for more
complex frequencies.

John

Anders Time said the following on 01/25/2008 07:23 AM: > What is the best way to generate a very stable 10.001MHz(low E-13 or > -110dBc/1Hz) to be to do high resolution heterodyne(Allan deviation) > measurements? > Using DDS? > Using PTS 500 or 250 synth and divide? Using HP 8662A and divide? > Some smart pll circuit by locking the 1000Hz to the reference in some way? > Thanks > Anders Rick Karlquist has published a design for a very low noise synthesizer designed for just this application. Unfortunately, I don't have a link to that handy, but it's on his website. I just took a look at some measurements I did on a PTS-250-SX51 (special version with low noise output to 25 MHz via an internal divider) and it looks like it would barely meet your requirements -- around 2x10e-13 at 1 second, and about -115 dBc/Hz at 1 Hz offset: http://www.febo.com/pages/pts_synth/images/pts-250-sx51-adev.png http://www.febo.com/pages/pts_synth/images/pts-250-sx51-spectrum.png However, that was at 10.000... MHz; the performance, particularly with respect to spurs, changes as the decimal dividers kick in for more complex frequencies. John

BG

Bruce Griffiths

Fri, Jan 25, 2008 1:39 PM

Anders Time wrote:

What is the best way to generate a very stable 10.001MHz(low E-13 or
-110dBc/1Hz) to be to do high resolution heterodyne(Allan deviation)
measurements?
Using DDS?
Using PTS 500 or 250 synth and divide? Using HP 8662A and divide?
Some smart pll circuit by locking the 1000Hz to the reference in some way?
Thanks
Anders

time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.

Anders

Its far easier to produce 9.999MHz cleanly than 10.001MHz

The simplest and quietest way is to use a pair of cascaded SSB mixers:
The first SSB mixer is an LSB mixer that subtracts (10MHz / 100) from
10MHz to produce 9.9MHz.

The second SSB mixer is a USB mixer that adds (9.9MHz/100) to 9.9MHz to
produce 9.999MHz.

i.e. 10MHz*(1 + 1/100)*(1-1/100) = 9.999MHz

Follow the USB mixer with a cleanup PLL using a low noise OCXO, however
you will need a custom crystal.

This is why NIST used a 10Hz offset with a 10MHz input and NIST + JPL
use a 100Hz offset with a 100MHz input no custom crystal is required its
easy enough to offset a standard 10MHz OCXO by 1ppm.

Process is similar:

9.99999MHz = 10.00MHz (1-1/1000)*(1+1/1000)

One could also use a USB mixer

10.001MHz = 10MHz*(1+1/10,000) but it may be more difficult to filter
out the residual 9.999MHz component in the USB output.

Synthesizers seem attractive, but in practice they have lots of spurs
that can interfere unless you choose a suitable offset like 123 Hz as
adopted by JPL to minimise synthesizers spurs when using a commercial
synthesizer.

Bruce

Anders Time wrote: > What is the best way to generate a very stable 10.001MHz(low E-13 or > -110dBc/1Hz) to be to do high resolution heterodyne(Allan deviation) > measurements? > Using DDS? > Using PTS 500 or 250 synth and divide? Using HP 8662A and divide? > Some smart pll circuit by locking the 1000Hz to the reference in some way? > Thanks > Anders > _______________________________________________ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. > > Anders Its far easier to produce 9.999MHz cleanly than 10.001MHz The simplest and quietest way is to use a pair of cascaded SSB mixers: The first SSB mixer is an LSB mixer that subtracts (10MHz / 100) from 10MHz to produce 9.9MHz. The second SSB mixer is a USB mixer that adds (9.9MHz/100) to 9.9MHz to produce 9.999MHz. i.e. 10MHz*(1 + 1/100)*(1-1/100) = 9.999MHz Follow the USB mixer with a cleanup PLL using a low noise OCXO, however you will need a custom crystal. This is why NIST used a 10Hz offset with a 10MHz input and NIST + JPL use a 100Hz offset with a 100MHz input no custom crystal is required its easy enough to offset a standard 10MHz OCXO by 1ppm. Process is similar: 9.99999MHz = 10.00MHz (1-1/1000)*(1+1/1000) One could also use a USB mixer 10.001MHz = 10MHz*(1+1/10,000) but it may be more difficult to filter out the residual 9.999MHz component in the USB output. Synthesizers seem attractive, but in practice they have lots of spurs that can interfere unless you choose a suitable offset like 123 Hz as adopted by JPL to minimise synthesizers spurs when using a commercial synthesizer. Bruce

R(

Richard (Rick) Karlquist

Fri, Jan 25, 2008 7:38 PM

See:

http://www.karlquist.com/FCS95.pdf

Or look at the 1995 FCS proceedings.

Rick Karlquist

John Ackermann N8UR wrote:

Anders Time said the following on 01/25/2008 07:23 AM:

What is the best way to generate a very stable 10.001MHz(low E-13 or
-110dBc/1Hz) to be to do high resolution heterodyne(Allan deviation)
measurements?
Using DDS?
Using PTS 500 or 250 synth and divide? Using HP 8662A and divide?
Some smart pll circuit by locking the 1000Hz to the reference in some way?
Thanks
Anders

Rick Karlquist has published a design for a very low noise synthesizer
designed for just this application. Unfortunately, I don't have a link
to that handy, but it's on his website.

I just took a look at some measurements I did on a PTS-250-SX51 (special
version with low noise output to 25 MHz via an internal divider) and it
looks like it would barely meet your requirements -- around 2x10e-13 at
1 second, and about -115 dBc/Hz at 1 Hz offset:

http://www.febo.com/pages/pts_synth/images/pts-250-sx51-adev.png
http://www.febo.com/pages/pts_synth/images/pts-250-sx51-spectrum.png

However, that was at 10.000... MHz; the performance, particularly with
respect to spurs, changes as the decimal dividers kick in for more
complex frequencies.

John

time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.

See: http://www.karlquist.com/FCS95.pdf Or look at the 1995 FCS proceedings. Rick Karlquist John Ackermann N8UR wrote: > Anders Time said the following on 01/25/2008 07:23 AM: >> What is the best way to generate a very stable 10.001MHz(low E-13 or >> -110dBc/1Hz) to be to do high resolution heterodyne(Allan deviation) >> measurements? >> Using DDS? >> Using PTS 500 or 250 synth and divide? Using HP 8662A and divide? >> Some smart pll circuit by locking the 1000Hz to the reference in some way? >> Thanks >> Anders > > Rick Karlquist has published a design for a very low noise synthesizer > designed for just this application. Unfortunately, I don't have a link > to that handy, but it's on his website. > > I just took a look at some measurements I did on a PTS-250-SX51 (special > version with low noise output to 25 MHz via an internal divider) and it > looks like it would barely meet your requirements -- around 2x10e-13 at > 1 second, and about -115 dBc/Hz at 1 Hz offset: > > http://www.febo.com/pages/pts_synth/images/pts-250-sx51-adev.png > http://www.febo.com/pages/pts_synth/images/pts-250-sx51-spectrum.png > > However, that was at 10.000... MHz; the performance, particularly with > respect to spurs, changes as the decimal dividers kick in for more > complex frequencies. > > John > > _______________________________________________ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. > >

BG

Bruce Griffiths

Fri, Jan 25, 2008 8:46 PM

The following paper details the effect of clock noise aliasing by
digital dividers:

http://tf.nist.gov/timefreq/general/pdf/1380.pdf

Bruce

The following paper details the effect of clock noise aliasing by digital dividers: http://tf.nist.gov/timefreq/general/pdf/1380.pdf Bruce

time-nuts@lists.febo.com

Generation of very stable 10.001MHz for heterodyne freq measurement