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View all threadsStarting FPGA development on Ettus N321
Hello,
I am trying to create a Vivado environment for the ettus 321, however, I am running into issues.
I navigated to uhd/fpga/usrp3/top/n3xx where there is a makefile which I assume creates the environment in Vivado. I run the makefile, but I end up with the error. It was successfully synthesized some of the netlists, but it fails on hb47_1to2, and I am not left with a vivado project I can open. I have pasted the error below. I am using Ubuntu 20.04, UHD 4.3.0, Vivado 2021.1
Thanks
Joe
---======================
BUILDER: Building IP hb47_1to2
---=======================
BUILDER: Staging IP in build directory...
BUILDER: Reserving IP location: /workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/hb47_1to2
BUILDER: Retargeting IP to part zynq/xc7z100/ffg900/-2...
BUILDER: Building IP...
[00:00:00] Executing command: vivado -mode batch -source workarea/uhd/fpga/usrp3/tools/scripts/viv_generate_ip.tcl -log hb47_1to2.log -nojournal
[00:00:05] Current task: Initialization +++ Current Phase: Starting
WARNING: [IP_Flow 19-2162] IP 'hb47_1to2' is locked:
CRITICAL WARNING: [filemgmt 20-1366] Unable to reset target(s) for the following file is locked: workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/hb47_1to2/hb47_1to2.xci
CRITICAL WARNING: [filemgmt 20-1365] Unable to generate target(s) for the following file is locked: workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/hb47_1to2/hb47_1to2.xci
[00:00:05] Current task: Initialization +++ Current Phase: Finished
[00:00:05] Executing Tcl: synth_design -top hb47_1to2 -part xc7z100ffg900-2 -mode out_of_context
[00:00:05] Starting Synthesis Command
WARNING: [Vivado_Tcl 4-391] The following IPs are missing output products for Synthesis target. These output products could be required for synthesis, please generate the output products using the generate_target or synth_ip command before running synth_design.
WARNING: [IP_Flow 19-2162] IP 'hb47_1to2' is locked:
[00:00:06] Current task: Synthesis +++ Current Phase: Starting
ERROR: [Designutils 20-414] HRTInvokeSpec : No Verilog or VHDL sources specified
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/hb47_1to2/hb47_1to2.xml'
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/hb47_1to2/hb47_1to2.xml'
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/hb47_1to2/hb47_1to2.xml'
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/hb47_1to2/hb47_1to2.xml'
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/hb47_1to2/hb47_1to2.xml'
ERROR: [Vivado 12-398] No designs are open
[00:00:06] Current task: Synthesis +++ Current Phase: Finished
[00:00:06] Process terminated. Status: Failure
---=======================
Warnings: 3
Critical Warnings: 7
Errors: 8
BUILDER: Releasing IP location: /workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/hb47_1to2
make[1]: *** [workarea/uhd/fpga/usrp3/top/n3xx/ip/hb47_1to2/Makefile.inc:19: IP_HB47_1TO2_TRGT] Error 1
make[1]: Leaving directory '/workarea/uhd/fpga/usrp3/top/n3xx'
make: *** [Makefile:90: N3X0_IP] Error 2
I am assuming you also sourced setupenv.sh in the n3xx directory?
If you remove the n3xx/build-ip/xc7z100ffg900-2/hb47_1to2 directory and try
again, does it still fail?
Brian
On Thu, Jan 12, 2023 at 6:35 PM jmaloyan@umass.edu wrote:
Hello,
I am trying to create a Vivado environment for the ettus 321, however, I
am running into issues.
I navigated to uhd/fpga/usrp3/top/n3xx where there is a makefile which I
assume creates the environment in Vivado. I run the makefile, but I end up
with the error. It was successfully synthesized some of the netlists, but
it fails on hb47_1to2, and I am not left with a vivado project I can open.
I have pasted the error below. I am using Ubuntu 20.04, UHD 4.3.0, Vivado
2021.1
Thanks
Joe
---======================
BUILDER: Building IP hb47_1to2
---=======================
BUILDER: Staging IP in build directory...
BUILDER: Reserving IP location:
/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/hb47_1to2
BUILDER: Retargeting IP to part zynq/xc7z100/ffg900/-2...
BUILDER: Building IP...
[00:00:00] Executing command: vivado -mode batch -source
workarea/uhd/fpga/usrp3/tools/scripts/viv_generate_ip.tcl -log
hb47_1to2.log -nojournal
[00:00:05] Current task: Initialization +++ Current Phase: Starting
WARNING: [IP_Flow 19-2162] IP 'hb47_1to2' is locked:
CRITICAL WARNING: [filemgmt 20-1366] Unable to reset target(s) for the
following file is locked:
workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/hb47_1to2/hb47_1to2.xci
CRITICAL WARNING: [filemgmt 20-1365] Unable to generate target(s) for the
following file is locked:
workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/hb47_1to2/hb47_1to2.xci
[00:00:05] Current task: Initialization +++ Current Phase: Finished
[00:00:05] Executing Tcl: synth_design -top hb47_1to2 -part
xc7z100ffg900-2 -mode out_of_context
[00:00:05] Starting Synthesis Command
WARNING: [Vivado_Tcl 4-391] The following IPs are missing output products
for Synthesis target. These output products could be required for
synthesis, please generate the output products using the generate_target or
synth_ip command before running synth_design.
WARNING: [IP_Flow 19-2162] IP 'hb47_1to2' is locked:
[00:00:06] Current task: Synthesis +++ Current Phase: Starting
ERROR: [Designutils 20-414] HRTInvokeSpec : No Verilog or VHDL sources
specified
ERROR: [Common 17-53] User Exception: No open design. Please open an
elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an
elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an
elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an
elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an
elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an
elaborated, synthesized or implemented design before executing this command.
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file
'/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/hb47_1to2/hb47_1to2.xml'
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file
'/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/hb47_1to2/hb47_1to2.xml'
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file
'/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/hb47_1to2/hb47_1to2.xml'
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file
'/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/hb47_1to2/hb47_1to2.xml'
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file
'/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/hb47_1to2/hb47_1to2.xml'
ERROR: [Vivado 12-398] No designs are open
[00:00:06] Current task: Synthesis +++ Current Phase: Finished
[00:00:06] Process terminated. Status: Failure
---=======================
Warnings: 3
Critical Warnings: 7
Errors: 8
BUILDER: Releasing IP location:
/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/hb47_1to2
make[1]: ***
[workarea/uhd/fpga/usrp3/top/n3xx/ip/hb47_1to2/Makefile.inc:19:
IP_HB47_1TO2_TRGT] Error 1
make[1]: Leaving directory '/workarea/uhd/fpga/usrp3/top/n3xx'
make: *** [Makefile:90: N3X0_IP] Error 2
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Hello,
I have run the setupenv.
build-ip is a folder that is made when the makefile(uhd/fpga/usrp3/top/n3xx/Makefile.inc) is run. Removing it does not do anything, but I did try commenting out include statements in the Makefile.
I tried commenting hb47_1to2 in the makefile, and it proceeded since it did not look for it. It asked for hb47_2to1, I commented that out and it moved on, but then it looked for something called axi_hb31, which I could not file in the include statements in the makefile.
The errors I get refer to an IP being “locked”, though I am unsure how to proceed from there. Some of the IPs have been built successfully
Vivado locks IP if it's been targeted for the wrong device, or generated
with the wrong version of the software.
Did you receive any warnings about the wrong version of Vivado being used?
Are you running in a clean UHD repo (git status shows no changes)?
I've run into this issue when things were targeted incorrectly and old
artifacts were still present during the build process.
Brian
On Fri, Jan 13, 2023 at 1:48 PM jmaloyan@umass.edu wrote:
Hello,
I have run the setupenv.
build-ip is a folder that is made when the
makefile(uhd/fpga/usrp3/top/n3xx/Makefile.inc) is run. Removing it does not
do anything, but I did try commenting out include statements in the
Makefile.
I tried commenting hb47_1to2 in the makefile, and it proceeded since it
did not look for it. It asked for hb47_2to1, I commented that out and it
moved on, but then it looked for something called axi_hb31, which I could
not file in the include statements in the makefile.
The errors I get refer to an IP being “locked”, though I am unsure how to
proceed from there. Some of the IPs have been built successfully
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When I type ‘git status’, it says there are no changes, I have dumped the output of git status below.…
HEAD detached at v4.3.0.0
Changes not staged for commit:
(use "git add <file>..." to update what will be committed)
(use "git restore <file>..." to discard changes in working directory)
modified: setupenv.sh
Untracked files:
(use "git add <file>..." to include in what will be committed)
ip/Makefile (copy).inc
no changes added to commit (use "git add" and/or "git commit -a")
i did have to edit the setupenv file however. In line 4 of the file, I changed it following from
VIVADO_VER_FULL=2021.1_AR76780 -> VIVADO_VER_FULL=2021.1
Before the edit, it gave this error…
Setting up a 64-bit FPGA build environment for the USRP-N3x0...
Vivado: Found (/tools/Xilinx/Vivado/2021.1/bin)
Vivado: ERROR! Requested version (2021.1_AR76780) not installed.
Install the required updates/patches and verify that the env variable
"VIVADO_VER_FULL" matches the version printed by "vivado -version"
vivado -version gave this output.
Vivado v2021.1 (64-bit)
SW Build 3247384 on Thu Jun 10 19:36:07 MDT 2021
IP Build 3246043 on Fri Jun 11 00:30:35 MDT 2021
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
Is there something else I have to install or edit?
Thanks,
Joe
Your git output says there are local modifications and then you describe
them but say it's all clean. Strange?
Anyway, yes - you need to install a patch from Xilinx. Follow this:
https://support.xilinx.com/s/article/76780?language=en_US
Download the ZIP file linked there and follow the installation instructions.
Also revert your modifications.
Brian
On Fri, Jan 13, 2023 at 5:06 PM jmaloyan@umass.edu wrote:
When I type ‘git status’, it says there are no changes, I have dumped the
output of git status below.…
HEAD detached at v4.3.0.0
Changes not staged for commit:
(use "git add <file>..." to update what will be committed)
(use "git restore <file>..." to discard changes in working directory)
modified: setupenv.sh
Untracked files:
(use "git add <file>..." to include in what will be committed)
ip/Makefile (copy).inc
no changes added to commit (use "git add" and/or "git commit -a")
i did have to edit the setupenv file however. In line 4 of the file, I
changed it following from
VIVADO_VER_FULL=2021.1_AR76780 -> VIVADO_VER_FULL=2021.1
Before the edit, it gave this error…
Setting up a 64-bit FPGA build environment for the USRP-N3x0...
Vivado: Found (/tools/Xilinx/Vivado/2021.1/bin)
Vivado: ERROR! Requested version (2021.1_AR76780) not installed.
Install the required updates/patches and verify that the env variable
"VIVADO_VER_FULL" matches the version printed by "vivado -version"
vivado -version gave this output.
Vivado v2021.1 (64-bit)
SW Build 3247384 on Thu Jun 10 19:36:07 MDT 2021
IP Build 3246043 on Fri Jun 11 00:30:35 MDT 2021
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
Is there something else I have to install or edit?
Thanks,
Joe
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This worked! Thanks.
Do you know if the makefile generates a vivado project (.xpr file) or does it only produce a final bitstream and its reports?
Glad it worked out.
It builds an in memory project only I believe. You can load up the GUI by
adding GUI=1 to the make command. From there, you can save off the project
if you like. You can also only check syntax with CHECK=1. Check the
bottom of the Makefile for some other supported command line options:
Good luck!
Brian
On Mon, Jan 16, 2023 at 12:39 PM jmaloyan@umass.edu wrote:
This worked! Thanks.
Do you know if the makefile generates a vivado project (.xpr file) or does
it only produce a final bitstream and its reports?
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I have the vivado project saved now, thanks for your help!
For the simulator files, I am a bit lost as to how it should be created?
I am following these instructions to build the simulator files https://files.ettus.com/manual/md_usrp3_sim_writing_sim_makefile.html. I tried running the viv_simulator with the xsim(and without) and I get this.
sudo make viv_simulator.mak xsim
make: Nothing to be done for 'viv_simulator.mak'.
make: *** No rule to make target 'xsim'. Stop.
What am I missing here. I also found a folder “/workarea/uhd/fpga/usrp3/top/n3xx/sim” with 6 directories, each with a Makefile and testbench systemverilog file. Is there something I should do with those? Is there a prebuilt simulation I can play around with, or do I need to make one from scratch?
Thanks,
Joe
On Tue, Jan 17, 2023 at 11:04 AM jmaloyan@umass.edu wrote:
I have the vivado project saved now, thanks for your help!
Glad it worked out for you.
For the simulator files, I am a bit lost as to how it should be created?
I am following these instructions to build the simulator files
https://files.ettus.com/manual/md_usrp3_sim_writing_sim_makefile.html. I
tried running the viv_simulator with the xsim(and without) and I get this.
sudo make viv_simulator.mak xsim
make: Nothing to be done for 'viv_simulator.mak'.
make: *** No rule to make target 'xsim'. Stop.
There's no reason to run this as root. Don't use sudo.
You should just be able to do make xsim and watch Vivado simulator run.
What am I missing here. I also found a folder
“/workarea/uhd/fpga/usrp3/top/n3xx/sim” with 6 directories, each with a
Makefile and testbench systemverilog file. Is there something I should do
with those? Is there a prebuilt simulation I can play around with, or do I
need to make one from scratch?
Look at these instructions for running the Makefiles:
https://files.ettus.com/manual/md_usrp3_sim_running_testbenches.html
Also, you should probably start a new email thread if you have other
questions instead of continuing down this one which seemingly has been
answered.
Brian