Hi I am implementing a zigbee transceiver on N210. The goal is to put the whole physical layer processing on the Xilinx FPGA. FPGA will have a custom designed processor, which will run the transceiver software image in RAM. Most of the documentation of UHD focuses on receiving the samples to a PC and processing it on PC. Can someone provide pointers on how to do on-board processing? If I want to burn a processors FPGA image and load the software into ram, how to do it?? Thanks and Regards Amanullah Ghazi

On 07/18/2011 02:01 AM, Amanullah wrote: > Hi > > > > I am implementing a zigbee transceiver on N210. The goal is to put the whole > physical layer processing on the Xilinx FPGA. FPGA will have a custom > designed processor, which will run the transceiver software image in RAM. > > > > Most of the documentation of UHD focuses on receiving the samples to a PC > and processing it on PC. Can someone provide pointers on how to do on-board > processing? If I want to burn a processors FPGA image and load the software > into ram, how to do it?? > > The top block for the FPGA in N210 is here: http://code.ettus.com/redmine/ettus/projects/uhd/repository/revisions/master/entry/fpga/usrp2/top/N2x0/u2plus_core.v Start at the top and work your way into the code. If you plug your own DSP blocks into the chain, see fpga/usrp2/sdr/lib/* for example http://code.ettus.com/redmine/ettus/projects/uhd/repository/revisions/master/entry/fpga/usrp2/sdr_lib/dsp_core_rx.v -Josh