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USRP B210 fpga build error

EC
Ethan C
Wed, Nov 29, 2023 8:41 AM

Hello,
I am trying to build the default B210 fpga project using Xilinx ISE just to
confirm I can do it before investing more time in a project. I downloaded
UHD 4.6 from the github repo and in ~uhd/fpga/usrp3/top/b200 set up the
Xilinx environment and built the fpga project

source /opt/Xilinx/14.7/ISE_DS/settings64.sh

make b210

I get an error "python: No such file or directory" during the "Generating
Report" part of the build like in the attached screenshots.

I don't quite understand the python line before the error, but I assume
it's calling check_timing.py with b200.twr as a parameter. check_timing.py
is in the expected location, not sure where build-B200//b200.twr is
supposed to be, but there is the touch command right before so it should be
in ~uhd/fpga/usrp3/top/b200.
The USRP B210 I am using wasn't connected when building the fpga project, I
assume that loading the new fpga project into the USRP can be done after
building it
I edited one file in ~uhd/fpga/usrp3/top/b200 by adding a comment so I
guess it's not truly default.
Is there something I'm missing or doing wrong?

Hello, I am trying to build the default B210 fpga project using Xilinx ISE just to confirm I can do it before investing more time in a project. I downloaded UHD 4.6 from the github repo and in ~uhd/fpga/usrp3/top/b200 set up the Xilinx environment and built the fpga project source /opt/Xilinx/14.7/ISE_DS/settings64.sh make b210 I get an error "python: No such file or directory" during the "Generating Report" part of the build like in the attached screenshots. I don't quite understand the python line before the error, but I assume it's calling check_timing.py with b200.twr as a parameter. check_timing.py is in the expected location, not sure where build-B200//b200.twr is supposed to be, but there is the touch command right before so it should be in ~uhd/fpga/usrp3/top/b200. The USRP B210 I am using wasn't connected when building the fpga project, I assume that loading the new fpga project into the USRP can be done after building it I edited one file in ~uhd/fpga/usrp3/top/b200 by adding a comment so I guess it's not truly default. Is there something I'm missing or doing wrong?
MD
Marcus D. Leech
Wed, Nov 29, 2023 8:54 AM

On 29/11/2023 03:41, Ethan C wrote:

Hello,
I am trying to build the default B210 fpga project using Xilinx ISE
just to confirm I can do it before investing more time in a project. I
downloaded UHD 4.6 from the github repo and in
~uhd/fpga/usrp3/top/b200 set up the Xilinx environment and built the
fpga project

source /opt/Xilinx/14.7/ISE_DS/settings64.sh

make b210

I get an error "python: No such file or directory" during the
"Generating Report" part of the build like in the attached screenshots.

I don't quite understand the python line before the error, but I
assume it's calling check_timing.py with b200.twr as a parameter.
check_timing.py is in the expected location, not sure where
build-B200//b200.twr is supposed to be, but there is the touch command
right before so it should be in ~uhd/fpga/usrp3/top/b200.
The USRP B210 I am using wasn't connected when building the fpga
project, I assume that loading the new fpga project into the USRP can
be done after building it
I edited one file in ~uhd/fpga/usrp3/top/b200 by adding a comment so I
guess it's not truly default.
Is there something I'm missing or doing wrong?

I looks like there's no program called "python" on your system.

Some distros require that the user decide which of the python2 or
python3 executables should be sym-linked to "python".

You probably haven't done that on your system.

On 29/11/2023 03:41, Ethan C wrote: > Hello, > I am trying to build the default B210 fpga project using Xilinx ISE > just to confirm I can do it before investing more time in a project. I > downloaded UHD 4.6 from the github repo and in > ~uhd/fpga/usrp3/top/b200 set up the Xilinx environment and built the > fpga project > > source /opt/Xilinx/14.7/ISE_DS/settings64.sh > > make b210 > > > I get an error "python: No such file or directory" during the > "Generating Report" part of the build like in the attached screenshots. > > > I don't quite understand the python line before the error, but I > assume it's calling check_timing.py with b200.twr as a parameter. > check_timing.py is in the expected location, not sure where > build-B200//b200.twr is supposed to be, but there is the touch command > right before so it should be in ~uhd/fpga/usrp3/top/b200. > The USRP B210 I am using wasn't connected when building the fpga > project, I assume that loading the new fpga project into the USRP can > be done after building it > I edited one file in ~uhd/fpga/usrp3/top/b200 by adding a comment so I > guess it's not truly default. > Is there something I'm missing or doing wrong? > > I looks like there's no program called "python" on your system. Some distros require that the user decide which of the python2 or python3 executables should be sym-linked to "python". You probably haven't done that on your system.
EC
Ethan C
Thu, Nov 30, 2023 8:41 PM

Yep that did the trick, thanks! Kind of embarrassingly simple but at least
I know for next time.

On Wed, Nov 29, 2023 at 12:55 AM Marcus D. Leech patchvonbraun@gmail.com
wrote:

On 29/11/2023 03:41, Ethan C wrote:

Hello,
I am trying to build the default B210 fpga project using Xilinx ISE just
to confirm I can do it before investing more time in a project. I
downloaded UHD 4.6 from the github repo and in ~uhd/fpga/usrp3/top/b200 set
up the Xilinx environment and built the fpga project

source /opt/Xilinx/14.7/ISE_DS/settings64.sh

make b210

I get an error "python: No such file or directory" during the "Generating
Report" part of the build like in the attached screenshots.

I don't quite understand the python line before the error, but I assume
it's calling check_timing.py with b200.twr as a parameter. check_timing.py
is in the expected location, not sure where build-B200//b200.twr is
supposed to be, but there is the touch command right before so it should be
in ~uhd/fpga/usrp3/top/b200.
The USRP B210 I am using wasn't connected when building the fpga project,
I assume that loading the new fpga project into the USRP can be done after
building it
I edited one file in ~uhd/fpga/usrp3/top/b200 by adding a comment so I
guess it's not truly default.
Is there something I'm missing or doing wrong?

I looks like there's no program called "python" on your system.

Some distros require that the user decide which of the python2 or python3
executables should be sym-linked to "python".

You probably haven't done that on your system.


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Yep that did the trick, thanks! Kind of embarrassingly simple but at least I know for next time. On Wed, Nov 29, 2023 at 12:55 AM Marcus D. Leech <patchvonbraun@gmail.com> wrote: > On 29/11/2023 03:41, Ethan C wrote: > > Hello, > I am trying to build the default B210 fpga project using Xilinx ISE just > to confirm I can do it before investing more time in a project. I > downloaded UHD 4.6 from the github repo and in ~uhd/fpga/usrp3/top/b200 set > up the Xilinx environment and built the fpga project > > source /opt/Xilinx/14.7/ISE_DS/settings64.sh > > make b210 > > I get an error "python: No such file or directory" during the "Generating > Report" part of the build like in the attached screenshots. > > > I don't quite understand the python line before the error, but I assume > it's calling check_timing.py with b200.twr as a parameter. check_timing.py > is in the expected location, not sure where build-B200//b200.twr is > supposed to be, but there is the touch command right before so it should be > in ~uhd/fpga/usrp3/top/b200. > The USRP B210 I am using wasn't connected when building the fpga project, > I assume that loading the new fpga project into the USRP can be done after > building it > I edited one file in ~uhd/fpga/usrp3/top/b200 by adding a comment so I > guess it's not truly default. > Is there something I'm missing or doing wrong? > > > I looks like there's no program called "python" on your system. > > Some distros require that the user decide which of the python2 or python3 > executables should be sym-linked to "python". > > You probably haven't done that on your system. > > > > _______________________________________________ > USRP-users mailing list -- usrp-users@lists.ettus.com > To unsubscribe send an email to usrp-users-leave@lists.ettus.com >