I attempted to build an FPGA image on the UHD-4.4 branch with Vivado v2021.1_AR76780 (64-bit) using:

make X410_X4_200 SYNTH=1 GUI=1

When the IP cores are generated, the following folder is not pulled in properly:

uhd/fpga/usrp3/top/x400/build-ip/xczu28drffvg1517-1e/xge_pcs_pma_ex/imports

As a temporary work-around, I was able to generate the example files from the xci file in

uhd/fpga/usrp3/top/x400/ip/xge_pcs_pma

and then copied the imports into my build directory and kicked off synthesis once again via GUI.

There was also a syntax error in x410_200_rfnoc_image_core.v. The forward ticks on line 182 were causing an issue:

localparam EDGE_TBL_FILE = `"`RFNOC_EDGE_TBL_FILE`";

Can someone provide some guidance? I’m not sure if I made a mistake when I pulled something in, or I’m one of the few that attempted to build the image.

Going forward, I need to make clock modifications and wanted to get a look at the clock structure in vivado to find the best path forward. To summarize, I need to change the 245.76 clocks to 204.8. I would also like to use the RFDC directly if possible (static configuration is fine). That would give me what I need without the DUC/DDC RFNoC blocks. If this isn’t feasible then I’ll need some rate-changing filters and additional clocks to adjust downstream.

- Ryan

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Hey Wade,

Here is the sequence of events:

• git clone from github
• git checkout UHD-4.4
• cd to x400 folder
• source setupenv.sh  (vivado 2021.1 with the AR patch applied)
• make cleanall
• make X410_X4_200 SYNTH=1 GUI=1  (<-- added those options so I could open the block design and take a peek at the clocks and RFDC config)

I am building on Linux Mint 20.3 Una, which is essentially Ubuntu 20.04 from a package perspective. I cut/pasted the dependency list from one of the setup docs, all of the packages were pulled in correctly, and I can talk to the X410 and run some of the example files.

I didn't make any modifications to the repo,  I want to get a default image successfully built before going any further. I've gotten through synthesis now, but haven't tried implementation and bitstream generation yet. I'm working from the GUI, so let me go back and check the RFNOC_EDGE_TBL_FILE definition and see exactly what's going on there.

Also, the "dev_config.json" file was missing from the x400 folder, not sure if that's another generated file, or just missing from the branch.  I copied that from the x300 folder.

Thanks,

Ryan

From: Wade Fife wade.fife@ettus.com
Sent: Thursday, August 24, 2023 11:12 PM
To: Seal, Ryan L. [US-US] ryan.seal@dynetics.com
Cc: usrp-users@lists.ettus.com usrp-users@lists.ettus.com
Subject: EXTERNAL: Re: [USRP-users] X410 FPGA build failure with UHD-4.4

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Hi Ryan,

What was the problem/error message that suggested that folder wasn't being pulled in properly? The "syntax error" implies that the `RFNOC_EDGE_TBLE_FILE definition isn't being set correctly, but the makefile should pass that in based on the target you're building.

Did you make modifications to the repo or run rfnoc_image_builder? If so, maybe try building the unmodified branch first to make sure everything is working. For example:

source setupenv.sh
make cleanall
make X410_X4_200

Also, what OS are you using to build on?

Wade

On Thu, Aug 24, 2023 at 11:16 AM <ryan.seal@dynetics.commailto:ryan.seal@dynetics.com> wrote:

I attempted to build an FPGA image on the UHD-4.4 branch with Vivado v2021.1_AR76780 (64-bit) using:

make X410_X4_200 SYNTH=1 GUI=1

When the IP cores are generated, the following folder is not pulled in properly:

uhd/fpga/usrp3/top/x400/build-ip/xczu28drffvg1517-1e/xge_pcs_pma_ex/imports

As a temporary work-around, I was able to generate the example files from the xci file in

uhd/fpga/usrp3/top/x400/ip/xge_pcs_pma

and then copied the imports into my build directory and kicked off synthesis once again via GUI.

There was also a syntax error in x410_200_rfnoc_image_core.v. The forward ticks on line 182 were causing an issue:

localparam EDGE_TBL_FILE = "RFNOC_EDGE_TBL_FILE`";

Can someone provide some guidance? I’m not sure if I made a mistake when I pulled something in, or I’m one of the few that attempted to build the image.

Going forward, I need to make clock modifications and wanted to get a look at the clock structure in vivado to find the best path forward. To summarize, I need to change the 245.76 clocks to 204.8. I would also like to use the RFDC directly if possible (static configuration is fine). That would give me what I need without the DUC/DDC RFNoC blocks. If this isn’t feasible then I’ll need some rate-changing filters and additional clocks to adjust downstream.

• Ryan

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Hello,

The undefined RFNOC_EDGE_TBL_FILE macro is a typical error when you try to build a Vivado project generated for X410.

The reason is that the macro is not passed correctly when synthesizing the Vivado project. My workaround was to use synth_design command generated by UHD X410 Makefile. An example:

synth_design -top x4xx -part xczu28dr-ffvg1517-2-e -verilog_define QSFP0_0=2 -verilog_define QSFP0_1=2 -verilog_define QSFP0_2=2 -verilog_define QSFP0_3=2 -verilog_define RFBW_200M=1 -verilog_define X410=1 -verilog_define GIT_HASH=32'hfbf186b7 -verilog_define RFNOC_EDGE_TBL_FILE=/home/user/RFSoC/uhd/fpga/usrp3/top/x400/x410_200_static_router.hex -verilog_define RFNOC_IMAGE_CORE_HDR=x410_200_rfnoc_image_core.vh -verilog_define UHD_FPGA_DIR=/home/user/RFSoC/uhd/fpga/usrp3/top/../.

I don’t remember exactly how I obtained it.

Best Regards,
Piotr Krysik

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I went back and manually restored the RFNOC_EDGE_TBL_FILE in my open design. The error went away, just a non-portable warning now, and it points to X410_200_static_router.hex. When the build initially bailed it probably had not put everything together yet, I think this issue is resolved.

The xge_pcs_pma_ex  example project did not create the imports folder when it was generated, I think that may be the root cause.

When I get a chance I'll make a new clone and build the IP cores and see if I can pinpoint that issue.

Thanks again,

Ryan

From: Seal, Ryan L. [US-US] RYAN.SEAL@dynetics.com
Sent: Friday, August 25, 2023 9:48 AM
To: Wade Fife wade.fife@ettus.com
Cc: usrp-users@lists.ettus.com usrp-users@lists.ettus.com
Subject: [USRP-users] Re: EXTERNAL: Re: X410 FPGA build failure with UHD-4.4

CAUTION: This email originated from outside of Leidos. Be cautious when clicking or opening content.

Hey Wade,

Here is the sequence of events:

• git clone from github
• git checkout UHD-4.4
• cd to x400 folder
• source setupenv.sh  (vivado 2021.1 with the AR patch applied)
• make cleanall
• make X410_X4_200 SYNTH=1 GUI=1  (<-- added those options so I could open the block design and take a peek at the clocks and RFDC config)

I am building on Linux Mint 20.3 Una, which is essentially Ubuntu 20.04 from a package perspective. I cut/pasted the dependency list from one of the setup docs, all of the packages were pulled in correctly, and I can talk to the X410 and run some of the example files.

I didn't make any modifications to the repo,  I want to get a default image successfully built before going any further. I've gotten through synthesis now, but haven't tried implementation and bitstream generation yet. I'm working from the GUI, so let me go back and check the RFNOC_EDGE_TBL_FILE definition and see exactly what's going on there.

Also, the "dev_config.json" file was missing from the x400 folder, not sure if that's another generated file, or just missing from the branch.  I copied that from the x300 folder.

Thanks,

Ryan

From: Wade Fife wade.fife@ettus.com
Sent: Thursday, August 24, 2023 11:12 PM
To: Seal, Ryan L. [US-US] ryan.seal@dynetics.com
Cc: usrp-users@lists.ettus.com usrp-users@lists.ettus.com
Subject: EXTERNAL: Re: [USRP-users] X410 FPGA build failure with UHD-4.4

CAUTION: This email originated from outside of Leidos. Be cautious when clicking or opening content.

Hi Ryan,

What was the problem/error message that suggested that folder wasn't being pulled in properly? The "syntax error" implies that the `RFNOC_EDGE_TBLE_FILE definition isn't being set correctly, but the makefile should pass that in based on the target you're building.

Did you make modifications to the repo or run rfnoc_image_builder? If so, maybe try building the unmodified branch first to make sure everything is working. For example:

source setupenv.sh
make cleanall
make X410_X4_200

Also, what OS are you using to build on?

Wade

On Thu, Aug 24, 2023 at 11:16 AM <ryan.seal@dynetics.commailto:ryan.seal@dynetics.com> wrote:

I attempted to build an FPGA image on the UHD-4.4 branch with Vivado v2021.1_AR76780 (64-bit) using:

make X410_X4_200 SYNTH=1 GUI=1

When the IP cores are generated, the following folder is not pulled in properly:

uhd/fpga/usrp3/top/x400/build-ip/xczu28drffvg1517-1e/xge_pcs_pma_ex/imports

As a temporary work-around, I was able to generate the example files from the xci file in

uhd/fpga/usrp3/top/x400/ip/xge_pcs_pma

and then copied the imports into my build directory and kicked off synthesis once again via GUI.

There was also a syntax error in x410_200_rfnoc_image_core.v. The forward ticks on line 182 were causing an issue:

localparam EDGE_TBL_FILE = "RFNOC_EDGE_TBL_FILE`";

Can someone provide some guidance? I’m not sure if I made a mistake when I pulled something in, or I’m one of the few that attempted to build the image.

Going forward, I need to make clock modifications and wanted to get a look at the clock structure in vivado to find the best path forward. To summarize, I need to change the 245.76 clocks to 204.8. I would also like to use the RFDC directly if possible (static configuration is fine). That would give me what I need without the DUC/DDC RFNoC blocks. If this isn’t feasible then I’ll need some rate-changing filters and additional clocks to adjust downstream.

• Ryan

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To unsubscribe send an email to usrp-users-leave@lists.ettus.commailto:usrp-users-leave@lists.ettus.com

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Hi Piotr,

That's exactly what I was attempting to do, build a Vivado project. I'll make a note of this.

Thanks for the tip.

Ryan

From: perper@o2.pl perper@o2.pl
Sent: Friday, August 25, 2023 9:52 AM
To: usrp-users@lists.ettus.com usrp-users@lists.ettus.com
Subject: EXTERNAL: [USRP-users] Re: X410 FPGA build failure with UHD-4.4

Hello,

The undefined RFNOC_EDGE_TBL_FILE macro is a typical error when you try to build a Vivado project generated for X410.

The reason is that the macro is not passed correctly when synthesizing the Vivado project. My workaround was to use synth_design command generated by UHD X410 Makefile. An example:

synth_design -top x4xx -part xczu28dr-ffvg1517-2-e -verilog_define QSFP0_0=2 -verilog_define QSFP0_1=2 -verilog_define QSFP0_2=2 -verilog_define QSFP0_3=2 -verilog_define RFBW_200M=1 -verilog_define X410=1 -verilog_define GIT_HASH=32'hfbf186b7 -verilog_define RFNOC_EDGE_TBL_FILE=/home/user/RFSoC/uhd/fpga/usrp3/top/x400/x410_200_static_router.hex -verilog_define RFNOC_IMAGE_CORE_HDR=x410_200_rfnoc_image_core.vh -verilog_define UHD_FPGA_DIR=/home/user/RFSoC/uhd/fpga/usrp3/top/../.

I don’t remember exactly how I obtained it.

Best Regards,
Piotr Krysik

Hello Wade,

The key is that Ryan tried to run synthesis again via Vivado gui.
From my experience this won’t work because some build parameters (like the mentioned macro definition) are passed together with synthesis command (synth_design).
If there is another way to make it work other than running the synth_design command with proper parameters manually - please tell how.

The project workflow with Vivado gui sometimes makes sense - i.e. when you want to experiment with modifications of block designs without having to export them for each synthesis run.

I also remember now one way to obtain the command that I shown in the previous post: you can find it by looking for “Command: synth_design“ in build.log that is in build-X410_X4_200 directory.

Best Regards,
Piotr Krysik