Dear All, I followed the build instruction for generation 3 on the website. All requirement and dependencies are fulfilled as well as Xilinx Vivado 2019.1. I would like to save the project in Vivado for future customization, therefore I ran "*make X310_HG GUI=1*". The makefile launch Vivado successfully, after configuration is done when I save the project using *save as *option in the Vivado. as I press generate bitstream in the Vivado, It automatically starts from synthesis phase, and it gives me the following errors in the synthesis phase: My UHD version is currently 3.14 LTS, I tried the FPGA source from different branches (e.g uhd3.14 LTS and uhd3.15 LTS) always results in the same errors. *[Synth 8-1766] cannot open include file ../../lib/io_port2/LvFpga_Chinch_Interface.vh ["/home/scoe-adm/Downloads/uhd-master/fpga/usrp3/top/x300/build-X310_HG/X310.srcs/sources_1/imports/usrp3/top/x300/x300.v":18]* *[Synth 8-2715] syntax error near ; ["/home/scoe-adm/Downloads/uhd-master/fpga/usrp3/top/x300/build-X310_HG/X310.srcs/sources_1/imports/usrp3/top/x300/x300.v":656]* *[Synth 8-1031] DMA_STREAM_WIDTH is not declared ["/home/scoe-adm/Downloads/uhd-master/fpga/usrp3/top/x300/build-X310_HG/X310.srcs/sources_1/imports/usrp3/top/x300/x300.v":664]* *[Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details* I'm absolutely blocked, any help is highly appreciated. Kind Regards, ----------------------------------------- Dipl.-Ing. Arash Jafari Phone: +43 650 844 3617 E-mail: arash.jafari.telecom@gmail.com

Arash, You might consider following the build process in the documentation after making your changes rather than trying to manage your own project. When you run "make X310_HG" it builds the FPGA in what Xilinx calls "non-project mode". That's the normal process we use. In your case, you created your own project from the results, effectively switching to "project mode". Looking at your error, the source of your problem is that it can't find the file LvFpga_Chinch_Interface.vh. According to the error message, the file x300.v is here: /home/scoe-adm/Downloads/uhd-master/fpga/usrp3/top/x300/build-X310_HG/X310.srcs/sources_1/imports/usrp3/top/x300/x300.v And it's trying to include "../../lib/io_port2/LvFpga_Chinch_Interface.vh", which, using its relative path, it expects to find here: /home/scoe-adm/Downloads/uhd-master/fpga/usrp3/top/x300/build-X310_HG/X310.srcs/sources_1/imports/usrp3/lib/io_port2/LvFpga_Chinch_Interface.vh I'm guessing that file is missing for you? It looks like you did something to import a copy of the code into your project instead of using the code in the original location, and perhaps some of the files were missed in that process. When I do a "save as" in Vivado to create a project, it leaves the files in their current location. Wade On Tue, Oct 6, 2020 at 2:00 AM Arash Jafari via USRP-users < usrp-users@lists.ettus.com> wrote: > Dear All, > > I followed the build instruction for generation 3 on the website. > All requirement and dependencies are fulfilled as well as Xilinx Vivado > 2019.1. > I would like to save the project in Vivado for future customization, > therefore I ran "*make X310_HG GUI=1*". > The makefile launch Vivado successfully, after configuration is done when > I save the project using *save as *option in the Vivado. as I press > generate bitstream in the Vivado, It automatically starts from synthesis > phase, and it gives me the following errors in the synthesis phase: > My UHD version is currently 3.14 LTS, I tried the FPGA source from > different branches (e.g uhd3.14 LTS and uhd3.15 LTS) always results in the > same errors. > > > > *[Synth 8-1766] cannot open include file > ../../lib/io_port2/LvFpga_Chinch_Interface.vh > ["/home/scoe-adm/Downloads/uhd-master/fpga/usrp3/top/x300/build-X310_HG/X310.srcs/sources_1/imports/usrp3/top/x300/x300.v":18]* > > > *[Synth 8-2715] syntax error near ; > ["/home/scoe-adm/Downloads/uhd-master/fpga/usrp3/top/x300/build-X310_HG/X310.srcs/sources_1/imports/usrp3/top/x300/x300.v":656]* > > > *[Synth 8-1031] DMA_STREAM_WIDTH is not declared > ["/home/scoe-adm/Downloads/uhd-master/fpga/usrp3/top/x300/build-X310_HG/X310.srcs/sources_1/imports/usrp3/top/x300/x300.v":664]* > > *[Common 17-69] Command failed: Synthesis failed - please see the console > or run log file for details* > > I'm absolutely blocked, any help is highly appreciated. > > Kind Regards, > > ----------------------------------------- > Dipl.-Ing. Arash Jafari > > Phone: +43 650 844 3617 > E-mail: arash.jafari.telecom@gmail.com > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >