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View all threadsUSRP x310 " ddr3_32bit: Code generation aborted: Unconfigured MIG instance"
Hello all,
I am trying to build an image for the usrp x310 in vivado 2015.4.
While building the ddr3_32bit IP for the project, I get a read out like
this:
---=======================
BUILDER: Building IP ddr3_32bit
---=======================
BUILDER: Staging IP in build directory...
Reserving IP location:
/home/rynmrlw/pybombs-prefix/src/uhd/fpga-src/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/ddr3_32bit
BUILDER: Retargeting IP to part xc7k410tffg900-2...
BUILDER: Building IP...
****** Vivado v2015.4 (64-bit)
**** SW Build 1412921 on Wed Nov 18 09:44:32 MST 2015
**** IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015
** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
source
/home/rynmrlw/pybombs-prefix/src/uhd/fpga-src/fpga/usrp3/top/../tools/scripts/viv_generate_ip.tcl
set xci_file $::env(XCI_FILE) ;
set part_name $::env(PART_NAME) ;
set gen_example_proj $::env(GEN_EXAMPLE) ;
set synth_ip $::env(SYNTH_IP) ;
set ip_name [file rootname [file tail $xci_file]] ;
file delete -force "$xci_file.out"
create_project -part $part_name -in_memory -ip
set_property target_simulator XSim [current_project]
add_files -norecurse -force $xci_file
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository
'/opt/Xilinx/Vivado/2015.4/data/ip'.
reset_target all [get_files $xci_file]
puts "BUILDER: Generating IP Target..."
BUILDER: Generating IP Target...
generate_target all [get_files $xci_file]
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP
'ddr3_32bit'...
*ERROR: [xilinx.com:ip:mig_7series:2.4-0] ddr3_32bit: Code generation
aborted: Unconfigured MIG instance*
*CRITICAL WARNING: [IP_Flow 19-1747] Failed to deliver file
'/opt/Xilinx/Vivado/2015.4/data/ip/xilinx/mig_7series_v2_4/xit/instantiation_template.xit': *
ERROR: [IP_Flow 19-167] Failed to deliver one or more file(s).
*ERROR: [IP_Flow 19-3505] IP Generation error: Failed to generate IP
'ddr3_32bit'. Failed to generate 'Verilog Instantiation Template' outputs: *
ERROR: [IP_Flow 19-98] Generation of the IP CORE failed.
Failed to generate IP 'ddr3_32bit'. Failed to generate 'Verilog
Instantiation Template' outputs:
INFO: [Common 17-206] Exiting Vivado at Fri Apr 8 02:41:13 2016...
Releasing IP location:
/home/rynmrlw/pybombs-prefix/src/uhd/fpga-src/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/ddr3_32bit
make[1]: ***
[/home/rynmrlw/pybombs-prefix/src/uhd/fpga-src/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/ddr3_32bit/ddr3_32bit.xci.out]
Error 1
make[1]: Leaving directory
`/home/rynmrlw/pybombs-prefix/src/uhd/fpga-src/fpga/usrp3/top/x300'
make: *** [X310_RFNOC_HGS] Error 2
I've upgraded the IP using the upgrade_ip.sh script in the ip folder. Is
there a specific version of Vivado (and IP) that I should be using? My
current vivado configurations are also included in this print out.
Best,
Ryan Marlow
Hi Ryan,
this is but a stab in the dark, but most things that make FPGA building
fail for me (if I didn't mess something up myself...) is when I forgot
to clean the build directory when updating/changing IP.
Is it possible that's the case here? Does "make cleanall; make X310_HGS"
(assuming that's the image flavour you're after) solve the issue?
Best regards,
Marcus
On 08.04.2016 08:58, Ryan Marlow via USRP-users wrote:
Hello all,
I am trying to build an image for the usrp x310 in vivado 2015.4.
While building the ddr3_32bit IP for the project, I get a read out
like this:
---=======================
BUILDER: Building IP ddr3_32bit
---=======================
BUILDER: Staging IP in build directory...
Reserving IP location:
/home/rynmrlw/pybombs-prefix/src/uhd/fpga-src/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/ddr3_32bit
BUILDER: Retargeting IP to part xc7k410tffg900-2...
BUILDER: Building IP...
****** Vivado v2015.4 (64-bit)
**** SW Build 1412921 on Wed Nov 18 09:44:32 MST 2015
**** IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015
** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
source
/home/rynmrlw/pybombs-prefix/src/uhd/fpga-src/fpga/usrp3/top/../tools/scripts/viv_generate_ip.tcl
# set xci_file $::env(XCI_FILE) ;
# set part_name $::env(PART_NAME) ;
# set gen_example_proj $::env(GEN_EXAMPLE) ;
# set synth_ip $::env(SYNTH_IP) ;
# set ip_name [file rootname [file tail $xci_file]] ;
# file delete -force "$xci_file.out"
# create_project -part $part_name -in_memory -ip
# set_property target_simulator XSim [current_project]
# add_files -norecurse -force $xci_file
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository
'/opt/Xilinx/Vivado/2015.4/data/ip'.
# reset_target all [get_files $xci_file]
# puts "BUILDER: Generating IP Target..."
BUILDER: Generating IP Target...
# generate_target all [get_files $xci_file]
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target
for IP 'ddr3_32bit'...
*ERROR: [xilinx.com:ip:mig_7series:2.4-0] ddr3_32bit: Code
generation aborted: Unconfigured MIG instance*
*CRITICAL WARNING: [IP_Flow 19-1747] Failed to deliver file
'/opt/Xilinx/Vivado/2015.4/data/ip/xilinx/mig_7series_v2_4/xit/instantiation_template.xit': *
*ERROR: [IP_Flow 19-167] Failed to deliver one or more file(s).*
*ERROR: [IP_Flow 19-3505] IP Generation error: Failed to generate
IP 'ddr3_32bit'. Failed to generate 'Verilog Instantiation
Template' outputs: *
*ERROR: [IP_Flow 19-98] Generation of the IP CORE failed.*
Failed to generate IP 'ddr3_32bit'. Failed to generate 'Verilog
Instantiation Template' outputs:
INFO: [Common 17-206] Exiting Vivado at Fri Apr 8 02:41:13 2016...
Releasing IP location:
/home/rynmrlw/pybombs-prefix/src/uhd/fpga-src/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/ddr3_32bit
make[1]: ***
[/home/rynmrlw/pybombs-prefix/src/uhd/fpga-src/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/ddr3_32bit/ddr3_32bit.xci.out]
Error 1
make[1]: Leaving directory
`/home/rynmrlw/pybombs-prefix/src/uhd/fpga-src/fpga/usrp3/top/x300'
make: *** [X310_RFNOC_HGS] Error 2
I've upgraded the IP using the upgrade_ip.sh script in the ip folder.
Is there a specific version of Vivado (and IP) that I should be using?
My current vivado configurations are also included in this print out.
Best,
Ryan Marlow
USRP-users mailing list
USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Hey All,
I believe I resolved the issue. I suppose the IP versions in Vivado 15.4
for the ddr3_32bit core is incompatible with the configuration provided in
the repo. I switched to the recommended 2015.2 version and the error did
not occur.
Best,
Ryan Marlow
On Fri, Apr 8, 2016 at 2:58 AM, Ryan Marlow rynmrlw@vt.edu wrote:
Hello all,
I am trying to build an image for the usrp x310 in vivado 2015.4.
While building the ddr3_32bit IP for the project, I get a read out like
this:
---=======================
BUILDER: Building IP ddr3_32bit
---=======================
BUILDER: Staging IP in build directory...
Reserving IP location:
/home/rynmrlw/pybombs-prefix/src/uhd/fpga-src/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/ddr3_32bit
BUILDER: Retargeting IP to part xc7k410tffg900-2...
BUILDER: Building IP...
****** Vivado v2015.4 (64-bit)
**** SW Build 1412921 on Wed Nov 18 09:44:32 MST 2015
**** IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015
** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
source
/home/rynmrlw/pybombs-prefix/src/uhd/fpga-src/fpga/usrp3/top/../tools/scripts/viv_generate_ip.tcl
set xci_file $::env(XCI_FILE) ;
set part_name $::env(PART_NAME) ;
set gen_example_proj $::env(GEN_EXAMPLE) ;
set synth_ip $::env(SYNTH_IP) ;
set ip_name [file rootname [file tail $xci_file]] ;
file delete -force "$xci_file.out"
create_project -part $part_name -in_memory -ip
set_property target_simulator XSim [current_project]
add_files -norecurse -force $xci_file
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository
'/opt/Xilinx/Vivado/2015.4/data/ip'.
reset_target all [get_files $xci_file]
puts "BUILDER: Generating IP Target..."
BUILDER: Generating IP Target...
generate_target all [get_files $xci_file]
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP
'ddr3_32bit'...
*ERROR: [xilinx.com:ip:mig_7series:2.4-0] ddr3_32bit: Code generation
aborted: Unconfigured MIG instance*
*CRITICAL WARNING: [IP_Flow 19-1747] Failed to deliver file
'/opt/Xilinx/Vivado/2015.4/data/ip/xilinx/mig_7series_v2_4/xit/instantiation_template.xit': *
ERROR: [IP_Flow 19-167] Failed to deliver one or more file(s).
*ERROR: [IP_Flow 19-3505] IP Generation error: Failed to generate IP
'ddr3_32bit'. Failed to generate 'Verilog Instantiation Template' outputs: *
ERROR: [IP_Flow 19-98] Generation of the IP CORE failed.
Failed to generate IP 'ddr3_32bit'. Failed to generate 'Verilog
Instantiation Template' outputs:
INFO: [Common 17-206] Exiting Vivado at Fri Apr 8 02:41:13 2016...
Releasing IP location:
/home/rynmrlw/pybombs-prefix/src/uhd/fpga-src/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/ddr3_32bit
make[1]: ***
[/home/rynmrlw/pybombs-prefix/src/uhd/fpga-src/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/ddr3_32bit/ddr3_32bit.xci.out]
Error 1
make[1]: Leaving directory
`/home/rynmrlw/pybombs-prefix/src/uhd/fpga-src/fpga/usrp3/top/x300'
make: *** [X310_RFNOC_HGS] Error 2
I've upgraded the IP using the upgrade_ip.sh script in the ip folder. Is
there a specific version of Vivado (and IP) that I should be using? My
current vivado configurations are also included in this print out.
Best,
Ryan Marlow