Hi, A question related to creating modified FPGA bitstreams using the Ettus source code. Based on Xilinx documentation, one needs to create a hardware handoff file (.hdf) file that the Xilinx SDK uses. If I try to create this .hdf file from the Vivado environment (for a project that builds successfully), Vivado complains it can't do that since It doesn't have the required file (IPI hardware definition file). Is this .hdf file not needed for the software development process prescribed by Ettus? Thanks Chintan

Hi Chintan, Can you describe what you want to accomplish? Are you trying to make a RFNoC block using HLS? Jonathon On Tue, Oct 4, 2016 at 1:27 PM, Patel, Chintan via USRP-users < usrp-users@lists.ettus.com> wrote: > Hi, > > > > A question related to creating modified FPGA bitstreams using the Ettus > source code. Based on Xilinx documentation, one needs to create a hardware > handoff file (.hdf) file that the Xilinx SDK uses. If I try to create this > .hdf file from the Vivado environment (for a project that builds > successfully), Vivado complains it can’t do that since It doesn’t have the > required file (IPI hardware definition file). Is this .hdf file not needed > for the software development process prescribed by Ettus? > > > > Thanks > > Chintan > > > > > > > > > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > >

Hi Jonathon, I am trying to understand how customizable the USRP/UHD framework is, particularly vis-à-vis making custom edits to the HDL/PL and being able to build an Zynq image (software) which has the “new” PL bitstream. When I try to correlate the Xilinx prescribed methodology for typical Zynq development flow to the source code available on the USRP git, I see there are some “discrepancies”. Specifically, Xilinx talks about creating/exporting a hardware definition file from Vivado that can then be used by their SDK to create the binary that contains the software + bitstream. But I think to create this hw definition file, Vivado seems to need a block design that describes the system – not the e310.v top level that is provided. I know that I can create new .bit files from Vivado and place them in the USRP file system which provides an easy mechanism to update the PL. But given the absence of the aforementioned hw definition file, my current theory is that the changes I make to the HDL/PL have to be such that the PS-PL interfaces are not changed. For e.g, I can add all the blocks I want in the DDC/DUC chain, but I can’t add a second HPC port to the PS-PL interface. Any clarifications will be much appreciated. Thanks Chintan From: Jonathon Pendlum [mailto:jonathon.pendlum@ettus.com] Sent: Tuesday, October 04, 2016 3:52 PM To: Patel, Chintan Cc: usrp-users@lists.ettus.com Subject: Re: [USRP-users] Vivado HDL-SDK hand-off Hi Chintan, Can you describe what you want to accomplish? Are you trying to make a RFNoC block using HLS? Jonathon On Tue, Oct 4, 2016 at 1:27 PM, Patel, Chintan via USRP-users <usrp-users@lists.ettus.com<mailto:usrp-users@lists.ettus.com>> wrote: Hi, A question related to creating modified FPGA bitstreams using the Ettus source code. Based on Xilinx documentation, one needs to create a hardware handoff file (.hdf) file that the Xilinx SDK uses. If I try to create this .hdf file from the Vivado environment (for a project that builds successfully), Vivado complains it can’t do that since It doesn’t have the required file (IPI hardware definition file). Is this .hdf file not needed for the software development process prescribed by Ettus? Thanks Chintan _______________________________________________ USRP-users mailing list USRP-users@lists.ettus.com<mailto:USRP-users@lists.ettus.com> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com

HI Chintan, You can make changes to the PS-PL interface. You'll need to edit the PS IP, which is usrp3/top/e300/ip/processing_system7_1/processing_system7_1.xci or usrp3/top/e300/ip/processing_system7_3/processing_system7_3.xci if you have a speed grade 3 E310. You'll also need to use the generated ps7_init.c and ps7_init.h files to generate a new bootloader via our OpenEmbedded build. Finally, you'll need to edit e3xx_ps.v and add the signals for the new interface. Jonathon On Wed, Oct 5, 2016 at 8:21 AM, Patel, Chintan <Chintan.Patel@commscope.com> wrote: > Hi Jonathon, > > > > I am trying to understand how customizable the USRP/UHD framework is, > particularly vis-à-vis making custom edits to the HDL/PL and being able to > build an Zynq image (software) which has the “new” PL bitstream. When I try > to correlate the Xilinx prescribed methodology for typical Zynq development > flow to the source code available on the USRP git, I see there are some > “discrepancies”. Specifically, Xilinx talks about creating/exporting a > hardware definition file from Vivado that can then be used by their SDK to > create the binary that contains the software + bitstream. But I think to > create this hw definition file, Vivado seems to need a block design that > describes the system – not the e310.v top level that is provided. > > > > I know that I can create new .bit files from Vivado and place them in the > USRP file system which provides an easy mechanism to update the PL. But > given the absence of the aforementioned hw definition file, my current > theory is that the changes I make to the HDL/PL have to be such that the > PS-PL interfaces are not changed. For e.g, I can add all the blocks I want > in the DDC/DUC chain, but I can’t add a second HPC port to the PS-PL > interface. > > > > Any clarifications will be much appreciated. > > > > Thanks > > Chintan > > > > *From:* Jonathon Pendlum [mailto:jonathon.pendlum@ettus.com] > *Sent:* Tuesday, October 04, 2016 3:52 PM > *To:* Patel, Chintan > *Cc:* usrp-users@lists.ettus.com > *Subject:* Re: [USRP-users] Vivado HDL-SDK hand-off > > > > Hi Chintan, > > > > Can you describe what you want to accomplish? Are you trying to make a > RFNoC block using HLS? > > > > > > > > Jonathon > > > > On Tue, Oct 4, 2016 at 1:27 PM, Patel, Chintan via USRP-users < > usrp-users@lists.ettus.com> wrote: > > Hi, > > > > A question related to creating modified FPGA bitstreams using the Ettus > source code. Based on Xilinx documentation, one needs to create a hardware > handoff file (.hdf) file that the Xilinx SDK uses. If I try to create this > .hdf file from the Vivado environment (for a project that builds > successfully), Vivado complains it can’t do that since It doesn’t have the > required file (IPI hardware definition file). Is this .hdf file not needed > for the software development process prescribed by Ettus? > > > > Thanks > > Chintan > > > > > > > > > > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > > >