Microstepper
prototype block-diagram, short list of chips in the implementation, and a
discussion on resolution now on ohwr.org:
https://ohwr.org/project/microstepper/wikis/Block-diagram
The obvious way to increase resolution (make the smallest frequency step
smaller) is to lower the IF.
I guess the limit is that we don't want the IF to feed-thru the
phase-detector and PLL all the way to a PN-spur in the output-OCXO.
My first prototype used 97 kHz IF and that gives a resolution of 1.7e-17.
Lowering that by /2 or /4 might be a good idea?
Other comments and ideas welcome!
Anders
my plan is to present our DIY version of this, an open hardware design, at
EFTF2020.
we have two AD9912:s clocked at 1GHz (derived from the maser) producing
two LO's that drive a mixer-board that locks an OCXO that feeds a PICDIV.
Anders
I took an initial look at your work.
No technical comments
The presentation of details is excellent. I had not seen this quality in a
wiki. Normally very simple. Look forward to a more detailed read.
Thank you for sharing.
Regards
Paul
WB8TSL
On Tue, Jan 14, 2020 at 1:59 AM Anders Wallin anders.e.e.wallin@gmail.com
wrote:
prototype block-diagram, short list of chips in the implementation, and a
discussion on resolution now on ohwr.org:
https://ohwr.org/project/microstepper/wikis/Block-diagram
The obvious way to increase resolution (make the smallest frequency step
smaller) is to lower the IF.
I guess the limit is that we don't want the IF to feed-thru the
phase-detector and PLL all the way to a PN-spur in the output-OCXO.
My first prototype used 97 kHz IF and that gives a resolution of 1.7e-17.
Lowering that by /2 or /4 might be a good idea?
Other comments and ideas welcome!
Anders
my plan is to present our DIY version of this, an open hardware design,
at
EFTF2020.
we have two AD9912:s clocked at 1GHz (derived from the maser) producing
two LO's that drive a mixer-board that locks an OCXO that feeds a PICDIV.
time-nuts mailing list -- time-nuts@lists.febo.com
To unsubscribe, go to
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and follow the instructions there.
Hi
The closer the beat note / spur / crud is to carrier, the bigger its effect on things
like ADEV and other timing issues. Indeed 97 KHz is pretty far out compared to
most of what people worry about. It is also quite far compared to the PLL bandwidth
of just about anything you normally would attach to a standard.
One would guess that the level of the spur would be same / same at lower IF
frequencies. If for some obscure reason the level changes, that could be an issue.
Maybe it gets lower :)
The rest of tthe argument gets into “nice numbers”. Cutting the IF in half would get you
into parts in 10^-18. From a round numbers standpoint, that has a lot of appeal.
Does it actually help in what you will be using the device for? The answer will
always be “that depends on what I’m doing ….”.
Bob
On Jan 14, 2020, at 1:58 AM, Anders Wallin anders.e.e.wallin@gmail.com wrote:
prototype block-diagram, short list of chips in the implementation, and a
discussion on resolution now on ohwr.org:
https://ohwr.org/project/microstepper/wikis/Block-diagram
The obvious way to increase resolution (make the smallest frequency step
smaller) is to lower the IF.
I guess the limit is that we don't want the IF to feed-thru the
phase-detector and PLL all the way to a PN-spur in the output-OCXO.
My first prototype used 97 kHz IF and that gives a resolution of 1.7e-17.
Lowering that by /2 or /4 might be a good idea?
Other comments and ideas welcome!
Anders
my plan is to present our DIY version of this, an open hardware design, at
EFTF2020.
we have two AD9912:s clocked at 1GHz (derived from the maser) producing
two LO's that drive a mixer-board that locks an OCXO that feeds a PICDIV.
time-nuts mailing list -- time-nuts@lists.febo.com
To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com
and follow the instructions there.
Hoi Anders,
On Tue, 14 Jan 2020 08:58:30 +0200
Anders Wallin anders.e.e.wallin@gmail.com wrote:
The obvious way to increase resolution (make the smallest frequency step
smaller) is to lower the IF.
I guess the limit is that we don't want the IF to feed-thru the
phase-detector and PLL all the way to a PN-spur in the output-OCXO.
My first prototype used 97 kHz IF and that gives a resolution of 1.7e-17.
Lowering that by /2 or /4 might be a good idea?
Other comments and ideas welcome!
Small question about your design choices:
Why do you start with ~400MHz for the DDS ouput frequencies?
Usually, a DDS offers lower noise for a :4 operation than
a D-FF frequency divider. Or is this not the case here?
It might be worthwile to replace DDS2 with a home-brewn one
using an FPGA, a 16bit DAC (e.g. LTC1668) and running it
directly off the 100MHz. The advantage is that you can build
a DDS core that has (almost) arbitrary bit-width and low distortion.
Thus you can decouple the frequency step resolution from the IF frequency
and get another knob you can turn freely. The use of a 16bit, "low speed"
DAC also decreases INL which in turn decreases harmonics (especially even
harmonics and thus flicker noise). The low speed also allows to play
tricks on the DAC word and get lower spurs, especially close in.
(I have an almost ready to use CORDIC implementation you could use, if needed)
And while you do that, you can use a second DAC to produce the 10MHz
signal and thus get lower noise than the MC12080 will give you.
Attila Kinali
--
It is upon moral qualities that a society is ultimately founded. All
the prosperity and technological sophistication in the world is of no
use without that foundation.
-- Miss Matheson, The Diamond Age, Neal Stephenson
There is now a first draft of the 'DDS-board', a 4-layer 100mm x 100mm PCB
with an ADF4351 PLL+VCO, and two AD9912 DDSs over here:
https://ohwr.org/project/microstepper/wikis/2020-06-02-DDSboard-draft
(kicad sources in the repository at
https://ohwr.org/project/microstepper/tree/master/ddsboard)
I will order a few prototype PCBs in a few weeks. In the meantime if anyone
has comments/suggests on the schematic or PCB from previous experience with
ADF4351, AD9912, or similar ICs then please let me know.
This DDS-board might be useful for other time/frequency tinkering also, in
addition to being a part of the second microstepper prototype I will try to
build within 1-3 months.
regards,
Anders
On Tue, Jan 14, 2020 at 8:58 AM Anders Wallin anders.e.e.wallin@gmail.com
wrote:
prototype block-diagram, short list of chips in the implementation, and a
discussion on resolution now on ohwr.org:
https://ohwr.org/project/microstepper/wikis/Block-diagram
The obvious way to increase resolution (make the smallest frequency step
smaller) is to lower the IF.
I guess the limit is that we don't want the IF to feed-thru the
phase-detector and PLL all the way to a PN-spur in the output-OCXO.
My first prototype used 97 kHz IF and that gives a resolution of 1.7e-17.
Lowering that by /2 or /4 might be a good idea?
Other comments and ideas welcome!
Anders
my plan is to present our DIY version of this, an open hardware design,
at EFTF2020.
we have two AD9912:s clocked at 1GHz (derived from the maser) producing
two LO's that drive a mixer-board that locks an OCXO that feeds a PICDIV.
In message CAPnVNRUEgRHAaGc6gp1=CjjFmd+=EjL8GhXqxXniy82CsOkn4A@mail.gmail.com, Anders Wallin writes:
I will order a few prototype PCBs in a few weeks. In the meantime if anyone
has comments/suggests on the schematic or PCB from previous experience with
ADF4351, AD9912, or similar ICs then please let me know.
I have played with this one:
http://www.rudius.net/oz2m/ngnb/dds.htm
as a synthesizer replacement in the HP5065, but your "dual" configuration
and the integrated 1GHz "pre-oscillator" would fit that purpose better,
so sign me up as interested buyer.
--
Poul-Henning Kamp | UNIX since Zilog Zeus 3.20
phk@FreeBSD.ORG | TCP/IP since RFC 956
FreeBSD committer | BSD since 4.3-tahoe
Never attribute to malice what can adequately be explained by incompetence.
Hello Anders,
I did the original design of the Crystek locked 1G CRO + 9912. Let me know if you have questions.
br
Christophe
http://distrinet.cs.kuleuven.be/people/showMember.do?memberID=u0013167
prof. dr. ir. Christophe Huygens IMEC-KULeuven-DistriNet
From: time-nuts time-nuts-bounces@lists.febo.com on behalf of Anders Wallin anders.e.e.wallin@gmail.com
Sent: Tuesday, June 2, 2020 7:38 AM
To: Discussion of precise time and frequency measurement
Subject: Re: [time-nuts] Microstepper
There is now a first draft of the 'DDS-board', a 4-layer 100mm x 100mm PCB
with an ADF4351 PLL+VCO, and two AD9912 DDSs over here:
https://ohwr.org/project/microstepper/wikis/2020-06-02-DDSboard-draft
(kicad sources in the repository at
https://ohwr.org/project/microstepper/tree/master/ddsboard)
I will order a few prototype PCBs in a few weeks. In the meantime if anyone
has comments/suggests on the schematic or PCB from previous experience with
ADF4351, AD9912, or similar ICs then please let me know.
This DDS-board might be useful for other time/frequency tinkering also, in
addition to being a part of the second microstepper prototype I will try to
build within 1-3 months.
regards,
Anders
On Tue, Jan 14, 2020 at 8:58 AM Anders Wallin anders.e.e.wallin@gmail.com
wrote:
prototype block-diagram, short list of chips in the implementation, and a
discussion on resolution now on ohwr.org:
https://ohwr.org/project/microstepper/wikis/Block-diagram
The obvious way to increase resolution (make the smallest frequency step
smaller) is to lower the IF.
I guess the limit is that we don't want the IF to feed-thru the
phase-detector and PLL all the way to a PN-spur in the output-OCXO.
My first prototype used 97 kHz IF and that gives a resolution of 1.7e-17.
Lowering that by /2 or /4 might be a good idea?
Other comments and ideas welcome!
Anders
my plan is to present our DIY version of this, an open hardware design,
at EFTF2020.
we have two AD9912:s clocked at 1GHz (derived from the maser) producing
two LO's that drive a mixer-board that locks an OCXO that feeds a PICDIV.
time-nuts mailing list -- time-nuts@lists.febo.com
To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com
and follow the instructions there.
On Tue, 02 Jun 2020 05:52:13 +0000
"Poul-Henning Kamp" phk@phk.freebsd.dk wrote:
I have played with this one:
http://www.rudius.net/oz2m/ngnb/dds.htm
as a synthesizer replacement in the HP5065, but your "dual" configuration
and the integrated 1GHz "pre-oscillator" would fit that purpose better,
so sign me up as interested buyer.
As a synthesizer for a Rb vapor cell standard, I would recommend going the
same way as INRIM did in [1]. It is by far the lowest noise synthesizer I have
seen for the relevant offset frequency range. Yes, it is a quite high effort
system. But it's also worth it. With this, you are sure that the short term
noise limit will not be the synthesiser anymore, but the lamp noise.
In a discussion, Claudio Calosso told me that the difficult part of the
whole system is getting to 1.6GHz. That part determines most of the perfomrance.
The rest was "quiet easy".
Attila Kinali
[1] "Simple-design ultra-low phase noise microwave frequency synthesizers for
high-performing Cs and Rb vapor-cell atomic clocks", by François, Calosso, Abdel Hafiz,
Micalizio, Boudot.
--
Science is made up of so many things that appear obvious
after they are explained. -- Pardot Kynes