Hi everyone: I'm trying to understand how the FPGA code works for the N210. More specifically, I was reading the signal processing code in the sdr_lib folder. Is there more documentation about this codes somewhere in the repo? For example, I was looking at the add2.v file. It seems to me that this code is adding two numbers and then dividing by two. Is that correct? Where is that used? I have doubts like this for other parts of the code so that's why I wanted to know about more documentation. I'd like to see why and how the dsp blocks (cordic, cic, etc) are implemented Thanks - Fernando

On 02/02/2013 05:17 PM, Fernando Quivira wrote: > Hi everyone: > > I'm trying to understand how the FPGA code works for the N210. More > specifically, I was reading the signal processing code in the sdr_lib > folder. Is there more documentation about this codes somewhere in the repo? Start here: http://code.ettus.com/redmine/ettus/projects/uhd/repository/revisions/master/entry/fpga/README.txt Each top level design is in usrp2/top/project. You can see where the dsp chains tie into the radio and transport, and internal routing. -josh > > Thanks > > - Fernando > > > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >

Thanks. I'll try to figure out the modules - Fernando On Sun, Feb 3, 2013 at 2:24 PM, Josh Blum <josh@ettus.com> wrote: > > > On 02/02/2013 05:17 PM, Fernando Quivira wrote: > > Hi everyone: > > > > I'm trying to understand how the FPGA code works for the N210. More > > specifically, I was reading the signal processing code in the sdr_lib > > folder. Is there more documentation about this codes somewhere in the > repo? > > Start here: > > http://code.ettus.com/redmine/ettus/projects/uhd/repository/revisions/master/entry/fpga/README.txt > > Each top level design is in usrp2/top/project. You can see where the dsp > chains tie into the radio and transport, and internal routing. > > -josh > > > > > Thanks > > > > - Fernando > > > > > > > > _______________________________________________ > > USRP-users mailing list > > USRP-users@lists.ettus.com > > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > > > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >

Thanks. I'll try to figure out the modules On Sun, Feb 3, 2013 at 2:24 PM, Josh Blum <josh@ettus.com> wrote: > > > On 02/02/2013 05:17 PM, Fernando Quivira wrote: > > Hi everyone: > > > > I'm trying to understand how the FPGA code works for the N210. More > > specifically, I was reading the signal processing code in the sdr_lib > > folder. Is there more documentation about this codes somewhere in the > repo? > > Start here: > > http://code.ettus.com/redmine/ettus/projects/uhd/repository/revisions/master/entry/fpga/README.txt > > Each top level design is in usrp2/top/project. You can see where the dsp > chains tie into the radio and transport, and internal routing. > > -josh > > > > > Thanks > > > > - Fernando > > > > > > > > _______________________________________________ > > USRP-users mailing list > > USRP-users@lists.ettus.com > > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > > > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >