I am trying to build the images and I have run into this error which looks like a problem with my tools. Has anyone seen this before? Mapping completed. See MAP report file "B100_map.mrp" for details. /opt/Xilinx/13.2/ISE_DS/ISE/bin/lin64/unwrapped/map: symbol lookup error: /opt/Xilinx/13.2/ISE_DS/ISE//lib/lin64/libXst_Core.so: undefined symbol: _ZN5antlr6BitSetD1Ev Process "Map" failed INFO:TclTasksC:1850 - process run : Generate Programming File is done. touch build-B100//B100.bin python /home/scap/uhd/fpga/usrp2/top/python/check_timing.py build-B100//B100.twr Traceback (most recent call last): File "/home/scap/uhd/fpga/usrp2/top/python/check_timing.py", line 33, in <module> if __name__=='__main__': map(print_timing_constraint_summary, sys.argv[1:]) File "/home/scap/uhd/fpga/usrp2/top/python/check_timing.py", line 25, in print_timing_constraint_summary for line in open(twr_file).readlines(): IOError: [Errno 2] No such file or directory: 'build-B100//B100.twr' make[1]: *** [bin] Error 1 make[1]: Leaving directory `/home/scap/uhd/fpga/usrp2/top/B100' make: *** [/home/scap/uhd/images/images/usrp_b100_fpga.bin] Error 2 scap@FPGADEV:~/uhd/images$ Jeff

Yes, it's a known Xilinx tool problem, though I've never encountered it. http://forums.xilinx.com/t5/Installation-and-Licensing/MAP-13-1-linking-error-on-runtime-at-exit/td-p/158232 On Oct 20, 2011, at 11:31 PM, Jeff Scaparra wrote: > I am trying to build the images and I have run into this error which looks like a problem with my tools. Has anyone seen this before? > > Mapping completed. > See MAP report file "B100_map.mrp" for details. > /opt/Xilinx/13.2/ISE_DS/ISE/bin/lin64/unwrapped/map: symbol lookup error: /opt/Xilinx/13.2/ISE_DS/ISE//lib/lin64/libXst_Core.so: undefined symbol: _ZN5antlr6BitSetD1Ev > > Process "Map" failed > INFO:TclTasksC:1850 - process run : Generate Programming File is done. > touch build-B100//B100.bin > python /home/scap/uhd/fpga/usrp2/top/python/check_timing.py build-B100//B100.twr > Traceback (most recent call last): > File "/home/scap/uhd/fpga/usrp2/top/python/check_timing.py", line 33, in <module> > if __name__=='__main__': map(print_timing_constraint_summary, sys.argv[1:]) > File "/home/scap/uhd/fpga/usrp2/top/python/check_timing.py", line 25, in print_timing_constraint_summary > for line in open(twr_file).readlines(): > IOError: [Errno 2] No such file or directory: 'build-B100//B100.twr' > make[1]: *** [bin] Error 1 > make[1]: Leaving directory `/home/scap/uhd/fpga/usrp2/top/B100' > make: *** [/home/scap/uhd/images/images/usrp_b100_fpga.bin] Error 2 > scap@FPGADEV:~/uhd/images$ > > > Jeff > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com