Martyn,

On 03/20/2016 07:26 PM, Martyn Smith wrote:

10 MHz and 32,768 kHz does not have an easy relationship.

10 MHz = 10^7 = 2^7 * 5^7 Hz
32768 Hz = 2^15

So, for 5^7 10 MHz cycles you will run 2^8 32,768 kHz cycles.

There is no way to divide down straight, and most DDSes only operates on
2^n basis which does not resolve the 5^7 factor accurately.

So, what you have to do is to use your divider (PIC in this case) to
consume an extra cycle here and there, with some logic to decide when.
Then you can accurately produce the frequency. A DDS with length being
10^7 (or at least have a length being multiple of 5^7) can produce it
directly. The alternating division factor can be made to work correctly,
but it will produce phase deviations, being up to a 32,768 kHz cycle
(more if you do it sloppy).

Think of it as accumulating the error and correct for it as you go, both
approaches do that.

Cheers,
Magnus

Hi Martyn,

This thread may also be of interest:
https://www.febo.com/pipermail/time-nuts/2008-October/034020.html
https://www.febo.com/pipermail/time-nuts/2012-February/063557.html

That's one way. Here two methods are tested, both on a PC and on a PIC:
http://www.leapsecond.com/tools/10m32k.c

When the PIC is in its 38 instruction loop the instantaneous output frequency is 32894.736842 Hz.
When the PIC is in its 39 instruction loop the instantaneous output frequency is 32051.282051 Hz.

Over exactly 1 second the average loop is 38.14697265625 instructions so the average frequency is 32768.000000 Hz. However, because of the PWM-like output, and depending on your gate time, your frequency counter may get confused and give readings between 32.1 kHz and 32.8 kHz, depending on which loop it sees at any given moment. If your frequency counter can generate exactly 1 second gate time in theory you should see an output of 32.768000000 kHz. What gate time are you using? What counter are you using? For testing a chip like this it's much better to use a totalizing or time interval counter instead of a frequency counter.

But here's an easier way to test your 10 MHz-to-32768 Hz divider:

1. divide your 10 MHz to 1 Hz with my PD07 (http://leapsecond.com/pic/src/pd07.asm)
2. divide same 10 MHz to 32768 Hz with your divider
3. divide said 32768 Hz to 1 Hz with my PD33 (http://leapsecond.com/pic/src/pd33.asm).
4. use a TIC to compare both 1 Hz signals

If the TI readings are constant you're done. If there's drift, then you have a cycle counting error.

No. I use PIC12F675 for all my dividers, but any PIC will work. You could use AVR too, adjusting the loop timings accordingly.

/tvb

----- Original Message -----
From: "Martyn Smith" martyn@ptsyst.com
To: time-nuts@febo.com
Cc: "'DM'" usmarees@hotmail.com
Sent: Sunday, March 20, 2016 11:26 AM
Subject: [time-nuts] 10 MHz to 32.768 kHz converter

Hello,

First of all quick apologies for sending an email last week without deleting all the old information from previous postings.

I have been playing around with producing 32.768 kHz from 10 MHz using a PIC chip.

I  have a real time clock calendar chip that requires a 32.768 kHz crystal.  I want to feed it with 10 MHz signal instead, so it is synchronised to my main 10 MHz in a frequency standard I am designing.

The method I’m using has been documented before where we have two loops running 9632 times through a 39 instruction loop and
55904 times through a 38 instruction loop, each time toggling the output pin.

I have done this and am getting approximately 32.768 kHz with the FM modulation as described by previous authors.

My question is should I expect exactly 32.768000000 kHz (obviously assuming we use the same 10 MHz to drive the divider and all test equipment)?

The closest I can get the 32.768 kHz is within about 0.1 Hz.

Does the actual model of PIC chip influence the accuracy?

Regards

Martyn

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and follow the instructions there.

How about Bresenham's Algorithm to alternate imperfect periods to
produce an average that matches any "perfect" period.

Refer to Bob Ammerman work to use Bresenham-type system for PIC MCU. He
was using the counter works in the background, either by polling or
Interrupt-Driven. So, the "SuperCycle" continues to run. The timer count
the value is stored in a 3-byte register that is decremented by the
software.

Regards,
Vlad

On 2016-03-20 14:26, Martyn Smith wrote:

--
WBW,

V.P.

In theory what is the best you can do using division of a 10MHz signal.
It's really not very good the period of the 32768 hz output will always be
"off".

I think the best way is to divide the 10MHz signal by some power of five
(like 78125) then use that to phase lock your 32768 oscillator.  In other
words use the 10MHz signal to discipline the 32K crystal.

On Sun, Mar 20, 2016 at 3:23 PM, Vlad time@patoka.org wrote:

--

Chris Albertson
Redondo Beach, California

Hi Chris,

Answer: with a 10 MHz PIC the best you can do in theory is +/- 200 ns on every 32 kHz edge, with no accumulating phase error, and perfect frequency accuracy for tau 1 s and above. And my divider meets theory. Details on how the "leap cycle" method works is in the source code:

http://leapsecond.com/pic/src/pd30.asm

True, whether a PIC or DDS or PLL the period will always be "off", to some degree, over some interval. So the question is how much is it off and when does it matter or what's the spec. It's standard phase noise, jitter, and ADEV stuff.

I'm not sure of Martyn's goal, but what I use these 10MHz-to-32kHz dividers for is replacing poor 32 kHz timekeeping with superb 10 MHz-based timekeeping (e.g., OCXO, Rb, Cs, GPSDO).

Lots of boards, sensors, loggers, RTC, quartz wall clocks use 32 kHz as a timebase. They either have a 1-pin input for a 32 kHz clock, or a 2-pin 32 kHz crystal. Either way, the PIC output can be used to drive the input pin, and voila! you've now improved the timekeeping by a factor of thousands to millions. These little PIC's run at 2 to 5 V so its very convenient.

Right, the extra complexity of a PLL and VCO-tunable 32 kHz tuning fork crystal (?) would be useful if the end goal were a 32 kHz, low phase noise, pure sinewave, 50R output, as if a bench instrument. But for driving 32 kHz CMOS IC timekeeping inputs, the low-jitter square wave from the PIC alone does the job.

/tvb

Hi Vlad,

Using dual periods is essentially what Martyn is doing. But I suspect it was serial rather than alternating (or maybe, interleaving is a better word), which caused his frequency readings to be unexpectedly anomalous.

The examples that Bob and Roman present are useful for timers, interrupts and time counting (e.g., 1 Hz or 50/60 Hz). But IIRC, it did not lend itself to generating relatively high frequency, low jitter outputs like 32 kHz, especially if you're using an 8-pin PIC and your budget is a 38 instruction loop. I would be interested, though, if you were able to use their approach to solve this particular 32 kHz problem.

Meanwhile the leap cycle solution works really well: 10 MHz in, 32768 Hz out. Simple. Give it a try:
http://leapsecond.com/pic/src/pd30.asm
http://leapsecond.com/pic/src/pd30.hex

To find (free, open) copies of Bresenham's original papers google for:
Bresenham 1963 "Algorithm for computer control of a digital plotter"
Bresenham 1977 "A Linear Algorithm for Incremental Digital Display of Circular Arcs"

And then, please also read this informative 2004 paper by Mitchell Harris:

"Line Drawing, Leap Years, and Euclid"
http://www.cs.tau.ac.il/~nachum/calendar-book/papers/bresenham.pdf

If you have further questions, let me know.

/tvb

Hi

Also consider the board space and power involved with a 32 KHz PLL. 32 KHz is not an off the shelf/ cheap / stock item for a packaged VCXO. If you start from 10 MHz and build a 32 KHz VCXO, your highest common factor is 128 Hz. That pretty much guarantees some level of spurs on your output with a simple loop. The most likely starting frequency would be 32.768 KHz x 5^N where N is in the 1 to 7 range. 4.096 and 20.48 MHz are better candidates for the VCXO than 32.768 KHz. This of course adds a bit more to the design.

Of course you could use a multiplier and drive a DDS chip. Then you could clean the DDS output up with a high frequency narrow band filter. Then you could divide the filter output down to 32 KHz …. Now we’re up to a couple of watts and a fairly big chunk of board space. There also is the minor issue of finding (or building) a filter.

Rather than doing it that easily, you could re-design the GPSDO. Build it from scratch with an output that divides directly to 32.768 KHz. It’s just a custom OCXO and a few years of coding. Now we’re up to a bit more power, a bit more size, and a few more parts to fail. There is the minor issue of cost as well…..

Yes, there are a lot of exciting ways to do this :)

Bob

On Sun, 20 Mar 2016 18:26:16 -0000
"Martyn Smith" martyn@ptsyst.com wrote:

Currently, all that has been discussed were digital solutions.
But what about using an analog approach?
If you have a 32kHz crystal oscillator, you can injection lock it
to the 10MHz signal, by dividing the 10MHz down to 128Hz, then use this
to form short (as in a couple of ns) pulses, which you then couple
to the crystal using a small (a couple of pF) capacitor.

Given that the crytsal has an accuracy of better than 100ppm, then
even a very weak coupling at 128Hz should be enough to keep it locked.
Upper bound on the jitter is 1/128Hz*100ppm=781ps (very simplified
calculation, but it should be definitly less than 1-2ns)

		Attila Kinali

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