On 07/11/2019 03:53 PM, lc wrote: > Thanks for all the response. > I should make my question more specific instead of using raw adc data > which is causing confusion. > The data I want to dump is (name based on b200.v) > rx_codec_d[11:0] which is directly from ADC > or > tx_data0[31:20] > tx_data0[15:4] > which are processed after b200_io > > But I don't want FPGA to further touch the data. > From Ian's suggestion, seems I need to > 1. configure the USRP so that sample_rate=master_clock_rate > 2. use a tuning policy that doesn’t imply the internal CORDIC > processor in the FPGA to perform any portion of the tuning. > > So my question is do I need to hack UHD in order to achieve item 2? > Or current matlab API could do this configuration. > > Thanks > Chao > > Item 2 above can be achieved with the normal tuning API in UHD. https://files.ettus.com/manual/classuhd_1_1usrp_1_1multi__usrp.html#a9b61448f392466e20572fdcb042e8ec6 and https://files.ettus.com/manual/structuhd_1_1tune__request__t.html