Hi all,

I went through the device recovery process explained here: https://kb.ettus.com/X300/X310_Device_Recovery, but I get the following error:

[INFO] [UHD] linux; GNU C++ version 9.3.0; Boost_107100; UHD_4.0.0.0-50-ge520e3ff

Unit: USRP X310 (3176C83, 192.168.30.2)

FPGA Image: /usr/local/share/uhd/images/usrp_x310_fpga_XG.bit failed.

Error: RuntimeError: Device reported an error during initialization.

I checked the error online and suggested to perform the recovery steps from the host itself (no switch in between) which I did but still getting the same error.

Has anyone know how to fix this issue?

Thanks,

Julian

sure,

1. I went through the device recovery because of the issue I am currently having. However, I noticed this issue fro the first time after using vivado ILA, I was programming the device using the hardware manager, debugging, making changes to the custom rfnoc block and creating images. When I finished using vivado for debugging and testing, I wanted to load the image using the python script uhd_image_loader but I noticed the device initialization issue, then I went through the device recovery process which did not work.

2. I can load a custom image or the default image via Vivado, connect rfnoc blocks, get the right information and display data with no issues. Also, the uhd_usrp_probe is working as shown below. But I can not restart the device because the image is not written EEPROM. If I do, UHD does not find any device, I have to use vivado to load images for now.

[INFO] [UHD] linux; GNU C++ version 9.3.0; Boost_107100; UHD_4.0.0.0-50-ge520e3ff
[INFO] [X300] X300 initialization sequence...
[INFO] [X300] Maximum frame size: 8000 bytes.
[INFO] [GPS] Found an internal GPSDO: LC_XO, Firmware Rev 0.929a
[INFO] [X300] Radio 1x clock: 200 MHz
  _____________________________________________________
 /
|       Device: X-Series Device
|     _____________________________________________________
|    /
|   |       Mboard: X310
|   |   revision: 11
|   |   revision_compat: 7
|   |   product: 30818
|   |   mac-addr0: 00:80:2f:22:ff:b4
|   |   mac-addr1: 00:80:2f:22:ff:b5
|   |   gateway: 192.168.10.1
|   |   ip-addr0: 192.168.10.2
|   |   subnet0: 255.255.255.0
|   |   ip-addr1: 192.168.20.2
|   |   subnet1: 255.255.255.0
|   |   ip-addr2: 192.168.30.2
|   |   subnet2: 255.255.255.0
|   |   ip-addr3: 192.168.40.2
|   |   subnet3: 255.255.255.0
|   |   serial: 3176C83
|   |   FW Version: 6.0
|   |   FPGA Version: 38.0
|   |   FPGA git hash: e520e3f-dirty
|   |
|   |   Time sources:  internal, external, gpsdo
|   |   Clock sources: internal, external, gpsdo
|   |   Sensors: gps_servo, gps_gprmc, gps_time, gps_gpgga, gps_locked, ref_locked
|     _____________________________________________________
|    /
|   |       RFNoC blocks on this device:
|   |
|   |   * 0/DDC#0
|   |   * 0/DDC#1
|   |   * 0/DUC#0
|   |   * 0/DUC#1
|   |   * 0/FFT#0
|   |   * 0/FFT#1
|   |   * 0/Radio#0
|   |   * 0/Radio#1
|     _____________________________________________________
|    /
|   |       Static connections on this device:
|   |
|   |   * 0/SEP#0:0==>0/DUC#0:0
|   |   * 0/DUC#0:0==>0/Radio#0:0
|   |   * 0/Radio#0:0==>0/DDC#0:0
|   |   * 0/DDC#0:0==>0/SEP#0:0
|   |   * 0/Radio#0:1==>0/DDC#0:1
|   |   * 0/DDC#0:1==>0/SEP#1:0
|   |   * 0/SEP#2:0==>0/DUC#1:0
|   |   * 0/DUC#1:0==>0/Radio#1:0
|   |   * 0/Radio#1:0==>0/DDC#1:0
|   |   * 0/DDC#1:0==>0/SEP#2:0
|   |   * 0/Radio#1:1==>0/DDC#1:1
|   |   * 0/DDC#1:1==>0/SEP#3:0
|   |   * 0/SEP#4:0==>0/FFT#0:0
|   |   * 0/FFT#0:0==>0/SEP#4:0
|   |   * 0/SEP#5:0==>0/FFT#1:0
|   |   * 0/FFT#1:0==>0/SEP#5:0
|     _____________________________________________________
|    /
|   |       TX Dboard: dboard
|   |   ID: UBX-160 v2 (0x007d)
|   |   Serial: 315EA14
|   |     _____________________________________________________
|   |    /
|   |   |       TX Frontend: 0
|   |   |   Name: UBX TX
|   |   |   Antennas: TX/RX, CAL
|   |   |   Sensors: lo_locked
|   |   |   Freq range: 10.000 to 6000.000 MHz
|   |   |   Gain range PGA0: 0.0 to 31.5 step 0.5 dB
|   |   |   Bandwidth range: 160000000.0 to 160000000.0 step 0.0 Hz
|   |   |   Connection Type: QI
|   |   |   Uses LO offset: No
|     _____________________________________________________
|    /
|   |       RX Dboard: dboard
|   |   ID: UBX-160 v2 (0x007e)
|   |   Serial: 315EA14
|   |     _____________________________________________________
|   |    /
|   |   |       RX Frontend: 0
|   |   |   Name: UBX RX
|   |   |   Antennas: TX/RX, RX2, CAL
|   |   |   Sensors: lo_locked
|   |   |   Freq range: 10.000 to 6000.000 MHz
|   |   |   Gain range PGA0: 0.0 to 31.5 step 0.5 dB
|   |   |   Bandwidth range: 160000000.0 to 160000000.0 step 0.0 Hz
|   |   |   Connection Type: IQ
|   |   |   Uses LO offset: No
|     _____________________________________________________
|    /
|   |       TX Dboard: dboard
|   |   ID: UBX-160 v2 (0x007d)
|   |   Serial: 3158364
|   |     _____________________________________________________
|   |    /
|   |   |       TX Frontend: 0
|   |   |   Name: UBX TX
|   |   |   Antennas: TX/RX, CAL
|   |   |   Sensors: lo_locked
|   |   |   Freq range: 10.000 to 6000.000 MHz
|   |   |   Gain range PGA0: 0.0 to 31.5 step 0.5 dB
|   |   |   Bandwidth range: 160000000.0 to 160000000.0 step 0.0 Hz
|   |   |   Connection Type: QI
|   |   |   Uses LO offset: No
|     _____________________________________________________
|    /
|   |       RX Dboard: dboard
|   |   ID: UBX-160 v2 (0x007e)
|   |   Serial: 3158364
|   |     _____________________________________________________
|   |    /
|   |   |       RX Frontend: 0
|   |   |   Name: UBX RX
|   |   |   Antennas: TX/RX, RX2, CAL
|   |   |   Sensors: lo_locked
|   |   |   Freq range: 10.000 to 6000.000 MHz
|   |   |   Gain range PGA0: 0.0 to 31.5 step 0.5 dB
|   |   |   Bandwidth range: 160000000.0 to 160000000.0 step 0.0 Hz
|   |   |   Connection Type: IQ
|   |   |   Uses LO offset: No

THANKS.

Hi Jonathon,

No I did not. The only thing I did was creating x300.bit bitstream files through vivado GUI, and programming the FPGA for ILA debugging, I was following the guide https://kb.ettus.com/Debugging_FPGA_images. I created a folder to save my projects and then after all the debugging, I used image builder without vivado GUI.

To load the image I used the image loader script and this issue came up, I decided to use the default image but the issue was still there.  I followed the steps of the recovery device guide but still the same.

Thanks

Hi,

I really need to recover this device, any help will be much appreciate it.

Thanks

Hello all,

I wonder if anyone can help me to recover this X310 from the issue I am currently experience.

Thanks

Hello all,

Did you manage to solve this and how?

I had similar problem, even without modifying the image. After an update of UHD drivers I loaded the new image using the image loader and something went wrong (so I could not use the x310 anymore). I get the same error as reported in the first post.

To make it working again I had to use Vivado to load the image. But it is not stored in ROM, so every time I switch off, I need to reload with Vivado. I tried different UHD versions and same result. No way to use the UHD image loader and store the image in ROM.

I also noticed that when I use GNURadio to generate even a simple signal, I get several underrun errors (lots of ‘U’) till the text buffer is completely full and the script crashes. I’m not sure it is related to the same issue, but (if I am not wrong) when we used the x310 at beginning it was working fine.

I was wondering it may be a problem of communication on the LAN (i.e. data transmission from PC to x310) which creates problems with both the image loading or data transmission (while it is OK loading images via JTAG).

Any idea?

Al

That is what I did (with the help of a colleague). It all went fine till almost the end. I managed to get the x310 working (e.g. answering to the uhd_usrp_probe command) after programming with Vivado.

But when I try the uhd_image_loader command at the end, I get the error above (exactly in the same way as explained by Julian in his first post).

So, I am now stuck with the x310 working but just if I do not switch it off, since the image in ROM is somewhat corrupted.

I’m not sure if the connection is not reliable. The x310 is directly connected to the PC via two 10G SFP+ cables. Is there a way to test this? I think there is another x310 in the lab, which I could use to test, but I do not want to mess up also that one, since it is not mine.

Al