Discussion and technical support related to USRP, UHD, RFNoC
View all threadsHi Everyone,
We would like to announce support in RFNoC for Xilinx's Vivado FPGA design
suite and the E310. To get these new features, simply fetch the latest
rfnoc-devel branch from our UHD git repository.
Most of the details for Vivado support were covered in our previous Vivado
announcement [1]. Specific to RFNoC, there is a small difference in the
build instructions (regarding makefile targets) so please also refer to our
Getting Started guide [2].
Also, E310 is now officially supported in RFNoC. Make sure to reference our
Known Issues & Missing Features [3] list to keep updated on our development
progress.
If you have any questions, please feel free to post them on this mailing
list or email the RFNoC team at rfnoc@ettus.com.
Jonathon Pendlum
Senior Software Engineer, Ettus Research
[1]
http://lists.ettus.com/pipermail/usrp-users_lists.ettus.com/2015-May/013835.html
[2] https://github.com/EttusResearch/uhd/wiki/RFNoC:-Getting-Started
[3]
https://github.com/EttusResearch/uhd/wiki#known-outstanding-bugs--missing-features