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Derek Kozel

Tue, Jul 18, 2017 9:26 PM

Hello all,

The 3.9.7 release of UHD has been posted. This is an update to the Long
Term Support series. There was one commit between the release candidate and
the final release. This added some safety checks to the
uhd_images_downloader script when using custom destination directories.

The tag for this release is located here:
https://github.com/EttusResearch/uhd/releases/tag/release_003_009_007

Installers for Windows and Fedora, as well as the source code, are
available here:
http://files.ettus.com/binaries/uhd/uhd_003.009.007-release/

And the LTS PPA for Ubuntu will have updated installers shortly:
https://launchpad.net/~ettusresearch/+archive/ubuntu/uhd-3.9.lts
https://launchpad.net/%7Eettusresearch/+archive/ubuntu/uhd-3.9.lts

There have been 28 commits since the last release which can be viewed here:
https://github.com/EttusResearch/uhd/compare/release_003_009_006...release_003_009_007

003.009.007

multi_usrp: Fixed get_normalized_tx_gain.
E300: Fix for streamer recreation issue
X300: Fix for network discovery, will now return early when correct
serial is found.
CBX: Fixed LO LPF behaviour in 1.5-2 GHz range.
UBX: Fixed dtor SIGABRT issue.
GPSDO: Improved detection.
Examples: Added channel param to samps to/from file. sync_to_gps exits
instead of uncaught throw.
C API: Fixed some missing fields in USRP info.
Docs: Many minor fixes.
CMake: Fixed GCC 4.4 compilation issue. Added ability to specify package
names.

Regards,
Derek

Hello all, The 3.9.7 release of UHD has been posted. This is an update to the Long Term Support series. There was one commit between the release candidate and the final release. This added some safety checks to the uhd_images_downloader script when using custom destination directories. The tag for this release is located here: https://github.com/EttusResearch/uhd/releases/tag/release_003_009_007 Installers for Windows and Fedora, as well as the source code, are available here: http://files.ettus.com/binaries/uhd/uhd_003.009.007-release/ And the LTS PPA for Ubuntu will have updated installers shortly: https://launchpad.net/~ettusresearch/+archive/ubuntu/uhd-3.9.lts <https://launchpad.net/%7Eettusresearch/+archive/ubuntu/uhd-3.9.lts> There have been 28 commits since the last release which can be viewed here: https://github.com/EttusResearch/uhd/compare/release_003_009_006...release_003_009_007 ## 003.009.007 * multi_usrp: Fixed get_normalized_tx_gain. * E300: Fix for streamer recreation issue * X300: Fix for network discovery, will now return early when correct serial is found. * CBX: Fixed LO LPF behaviour in 1.5-2 GHz range. * UBX: Fixed dtor SIGABRT issue. * GPSDO: Improved detection. * Examples: Added channel param to samps to/from file. sync_to_gps exits instead of uncaught throw. * C API: Fixed some missing fields in USRP info. * Docs: Many minor fixes. * CMake: Fixed GCC 4.4 compilation issue. Added ability to specify package names. Regards, Derek

EL

Estrada Lupianez, Jenniffer Marie

Tue, Jul 18, 2017 9:41 PM

Hi,

Can anyone point to any documentation or give some insight on how the E310 FPGA Verilog code design is laid out? I am not familiar with Verilog, and just extrapolating from what I understand from VHDL. What is the top level module? The e310.v file? What is the structure? I cannot find any documentation on the FPGA code other than the build instructions found here:

https://files.ettus.com/manual/md_usrp3_build_instructions.html and the comments in the verilog code itself. Is there anything else in terms of documentation?

Thank you,

Jenn

Hi, Can anyone point to any documentation or give some insight on how the E310 FPGA Verilog code design is laid out? I am not familiar with Verilog, and just extrapolating from what I understand from VHDL. What is the top level module? The e310.v file? What is the structure? I cannot find any documentation on the FPGA code other than the build instructions found here: https://files.ettus.com/manual/md_usrp3_build_instructions.html and the comments in the verilog code itself. Is there anything else in terms of documentation? Thank you, Jenn

MB

Martin Braun

Tue, Jul 18, 2017 11:07 PM

On 07/18/2017 02:41 PM, Estrada Lupianez, Jenniffer Marie via USRP-users
wrote:

Can anyone point to any documentation or give some insight on how the
E310 FPGA Verilog code design is laid out? I am not familiar with
Verilog, and just extrapolating from what I understand from VHDL. What
is the top level module? The e310.v file? What is the structure? I
cannot find any documentation on the FPGA code other than the build
instructions found here:

https://files.ettus.com/manual/md_usrp3_build_instructions.html and the
comments in the verilog code itself. Is there anything else in terms of
documentation?

Hi Jenn,

that's pretty much it. If you know VHDL, you'll have very little trouble
understanding Verilog though.

e310.v is the top-level. E310-specific modules are also in
usrp3/top/e310. We also pull in a lot of modules from usrp3/lib/*.

Cheers,
Martin

On 07/18/2017 02:41 PM, Estrada Lupianez, Jenniffer Marie via USRP-users wrote: > Can anyone point to any documentation or give some insight on how the > E310 FPGA Verilog code design is laid out? I am not familiar with > Verilog, and just extrapolating from what I understand from VHDL. What > is the top level module? The e310.v file? What is the structure? I > cannot find any documentation on the FPGA code other than the build > instructions found here: > > https://files.ettus.com/manual/md_usrp3_build_instructions.html and the > comments in the verilog code itself. Is there anything else in terms of > documentation? Hi Jenn, that's pretty much it. If you know VHDL, you'll have very little trouble understanding Verilog though. e310.v is the top-level. E310-specific modules are also in usrp3/top/e310. We also pull in a lot of modules from usrp3/lib/*. Cheers, Martin

usrp-users@lists.ettus.com

3.9.7 Release Announcement

003.009.007