In the body of an RFNOC block code, I had a for in for and calculation but when I want to synthesize it I was faced with a clock warning in FPGA. When I comment on this section this error is disappeared... So when I used a delay with tag # in some cases warning is removed... I:Errors: [00:04:49] Current task: Synthesis +++ Current Phase: Starting CRITICAL WARNING: [Constraints 18-1056] Clock 'FPGA_CLK' completely overrides clock 'FPGA_CLK_p'. II: Code section: for(i=0;i<32;i=i+1) begin d_i_buffer = d_i_buffer>>i;//shift samples buffer d_q_buffer = d_q_buffer>>i;//shift samples buffer for(j=0; j<96; j=j+1) begin temp_i_mult_result = temp_i_mult_result + d_i_buffer[j]*d_i_p_buffer[j]; temp_q_mult_result = temp_q_mult_result + d_q_buffer[j]*d_q_p_buffer[j]; end //#300 c_td[i]=temp_i_mult_result+temp_q_mult_result; end