Perry,

The bad part of your "solution", that you seem to be missing is the
BFO will not be locked or referenced to any standard but itself.  If
that is acceptable to you, then there is no need to reference your 3586
to anything but itself.... rendering the entire subject void to you.

The DDS solution makes the BFO frequency, which is very important in using
audio solutions to frequency measurement with 3586 referenced to the same
standard as the rest of the unit.  The small offset (not error) is easily
removed by simply subtracting, or adding it when figuring the result.  It
is constant, and will never change.

Unlike simply stabilizing the BFO crystal as you propose.

-Chuck Harris

Perry Sandeen wrote:

On Sat, Apr 02, 2011 at 04:13:55PM -0400, Chuck Harris wrote:

Has anyone given any thought to an alternative - phase locking

the original BFO Xtals with a very narrow bandwidth loop to something
derived from the 10 Mhz standard in such a way that the final frequency
of the BFO comes out exact ?  Looks to me (superficially without looking
at the schematic carefully) like this might be possible too...

--
Dave Emery N1PRE/AE, die@dieconsulting.com  DIE Consulting, Weston, Mass 02493
"An empty zombie mind with a forlorn barely readable weatherbeaten
'For Rent' sign still vainly flapping outside on the weed encrusted pole - in
celebration of what could have been, but wasn't and is not to be now either."

On Mon, Apr 04, 2011 at 02:00:14AM -0400, David I. Emery wrote:

To elaborate a tiny bit, if you divide 10 MHz to 25 HZ you could

use that as the reference for a classic PLL loop that stabilized the
crystals with a varactor... provided of course suitable low pass
filtering was used.  There are also approaches involving doing early
late sampling of the BFOs on selected edges of the 10 MHz clock which
could be done more digitally in a FPGA.

I presume one can pull the existing crystals enough with some hacking

of the oscillator to add a varactor...

This would avoid a non integer frequency setting where the DDS

approach does not (unless you multiply by 3 to 30 MHz first I think).

--
Dave Emery N1PRE/AE, die@dieconsulting.com  DIE Consulting, Weston, Mass 02493
"An empty zombie mind with a forlorn barely readable weatherbeaten
'For Rent' sign still vainly flapping outside on the weed encrusted pole - in
celebration of what could have been, but wasn't and is not to be now either."

Basically, the higher the division ratio in a PLL synthesizer,
which is what you are describing, the greater the phase noise.

You can think of it this way: Both the reference, and the oscillator
being controlled, need to be divided down to some common frequency
that you feed to the phase detector.  The entire time the counter is
counting up the cycles to get you a cycle of that common frequency,
the oscillator is not being disciplined.  It is only after the
count gets done that the phase detector can compare the two signals
and create a correction correct for the error in the oscillator.

The DDS is essentially a hardware solution to finding a suitable
divider ratio to convert one frequency into another.

-Chuck Harris

David I. Emery wrote:

"Basically, the higher the division ratio in a PLL synthesizer,
which is what you are describing, the greater the phase noise."

In that case, that may not be a problem. Since the oscillator is a crystal, phase noise should be low enough.

One other issue is that most crystals only want to move in one direction (with the varactor pulling trick), so if it is on the wrong side of where you want it, that won't work.

Otherwise, I have been thinking about that myself.

Didier KO4BB

Sent from my BlackBerry Wireless thingy while I do other things...

-----Original Message-----
From: Chuck Harris cfharris@erols.com
Sender: time-nuts-bounces@febo.com
Date: Mon, 04 Apr 2011 07:19:38
To: Discussion of precise time and frequency measurementtime-nuts@febo.com
Reply-To: Discussion of precise time and frequency measurement
time-nuts@febo.com
Subject: Re: [time-nuts] HP 3586 entirely referenced to 10MHz: A solution II

Basically, the higher the division ratio in a PLL synthesizer,
which is what you are describing, the greater the phase noise.

You can think of it this way: Both the reference, and the oscillator
being controlled, need to be divided down to some common frequency
that you feed to the phase detector.  The entire time the counter is
counting up the cycles to get you a cycle of that common frequency,
the oscillator is not being disciplined.  It is only after the
count gets done that the phase detector can compare the two signals
and create a correction correct for the error in the oscillator.

The DDS is essentially a hardware solution to finding a suitable
divider ratio to convert one frequency into another.

-Chuck Harris

David I. Emery wrote:

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and follow the instructions there.

Hi Didier,

If you want to convert the Xtal to a VCO, you will have to adjust the parallel
capacitance so that the crystal can get above the desired frequency, and then
design the varactor circuit so that it can pull from there to below the desired
frequency...which should be possible if the crystal was capable of being tuned
on frequency.

The crystal might be high enough Q to run in a PLL with a very high division ratio,
but I would still expect it to hiccup around about the period of the divider.... but
as you say, it might not matter.

The DDS works out to be such a simple solution, I think the minuscule offset is
hardly worth getting worked up over.

-Chuck

shalimr9@gmail.com wrote:

Hello Didier;

I don't have a copy of the schematic however I was
wondering if there are trim caps installed for these
crystals?? If so, then a varactor can tune above and
below in place of the mechanical cap if you remove it.
Undoubtedly there is some loading cap in the circuit
that could be tweaked a tad. Crystals drift over time
though, this could have an effect on this concept. It
may be that they have already drifted too far to tweak
with the VCO concept.

Also, there are many ways that a PLL ideas interact
with phase noise. If the PLL reference source is quieter
than the intrinsic noise of the VCO then the loop band
width does govern the close in noise spectrum. However,
there are many systems wherein the reference bandwidth
is very small and the VCO noise governsl. Take for
instance the PPS control of the GPSDO OXCO. The PPS
frequency reference is unable to reduce the noise of
the OXCO above about one half Hz, so the ultimate phase
noise above that frequency is that of the oscillator itself.
This can be a creative brain buster when working on
designs for these ideas.

My vote is to do a DDS synthesizer, this is a fine evolution
low in cost and easy to implement, to displace approximate
oscillators. What frequencies are you generating?

Regards;

Greg

On 4/4/2011 7:29 AM, Chuck Harris wrote:

On Mon, Apr 04, 2011 at 07:19:38AM -0400, Chuck Harris wrote:

No question about that, indeed.

But I am talking about a very low bandwidth loop (presumably

well under 1 HZ should work) which means the phase noise contribution
from the dividers and reference should be only inside that 1 Hz
bandpass. Outside of that the original crystal oscillator phase noise
should control, and while this won't improve that it also won't make it
any worse.

True, but I am pretty sure the original crystal oscillator (even

modified with a varactor for tuning) was not phase-noisier than the rest
of the instruments LOs.  It is, after all, a LF crystal oscillator
running at 13 or 17 KHz with presumably a high Q crystal which shouldn't
to the first order have unreasonable phase noise in the band around it.
The original problem was that this oscillator was not locked to a
reference and could drift a few tenths of a HZ (and maybe even Hz)
randomly with temp - not that it had too much phase noise.

I do understand DDSes.

--
Dave Emery N1PRE/AE, die@dieconsulting.com  DIE Consulting, Weston, Mass 02493
"An empty zombie mind with a forlorn barely readable weatherbeaten
'For Rent' sign still vainly flapping outside on the weed encrusted pole - in
celebration of what could have been, but wasn't and is not to be now either."

I am thinking the answer is not the interesting thread.
Its yes, that approach was considered.
I can't speak for Bert but the issue has been understood for a long time
actually. At least 10 years since my first purchase.

When I consider a problem I tend to look at the trade offs trade offs. The
ability to actually be reproduced, simple, parts availability, low cost,
stable, and a lot of other factors. Kind of would anyone else ever build
something like X.

So when FPGAs get introduced into the thread it starts to change the
complexity of the project and the likelihood of very few actually having the
ability to design or enhance and then burn the chip.

The is a heck of answer to a tough problem at a cost of $ 8 total for both
chips.

Can be improved, gets more difficult as you improve it. Like everything
else.
Regards
Paul
WB8TSL

On Mon, Apr 4, 2011 at 5:33 PM, David I. Emery die@dieconsulting.comwrote: