Hi USRP users, I am trying to build a gain block on USRP X410. When I tried to build bitstream for X410_XG_100, I got the following errors. Seems some IP is locked for USRP X410. Does that mean I need to purchase the IPs for building bitstream? It's odd to me that we still need to buy specific IPs to build bitsstream with RFNoC. How can I build a bitstream for X410? Thanks in advance. Environment successfully initialized. BUILDER: Checking tools... * GNU bash, version 5.0.17(1)-release (x86_64-pc-linux-gnu) * Python 3.8.10 * Vivado v2019.1 (64-bit) ======================================================== BUILDER: Building IP xge_pcs_pma ======================================================== BUILDER: Staging IP in build directory... BUILDER: Reserving IP location: /uhd/fpga/usrp3/top/x400/build-ip/xczu28drffvg1517-1e/xge_pcs_pma BUILDER: Retargeting IP to part zynquplusRFSOC/xczu28dr/ffvg1517/-1/e... BUILDER: Building IP... [00:00:00] Executing command: vivado -mode batch -source /uhd/fpga/usrp3/tools/scripts/viv_generate_ip.tcl -log xge_pcs_pma.log -nojournal WARNING: [IP_Flow 19-2162] IP 'xge_pcs_pma' is locked: CRITICAL WARNING: [filemgmt 20-1366] Unable to reset target(s) for the following file is locked: /uhd/fpga/usrp3/top/x400/build-ip/xczu28drffvg1517-1e/xge_pcs_pma/xge_pcs_pma.xci CRITICAL WARNING: [filemgmt 20-1365] Unable to generate target(s) for the following file is locked: /uhd/fpga/usrp3/top/x400/build-ip/xczu28drffvg1517-1e/xge_pcs_pma/xge_pcs_pma.xci [00:00:09] Current task: Initialization +++ Current Phase: Starting [00:00:09] Current task: Initialization +++ Current Phase: Finished [00:00:09] Executing Tcl: synth_design -top xge_pcs_pma -part xczu28dr-ffvg1517-1-e -mode out_of_context [00:00:09] Starting Synthesis Command WARNING: [Vivado_Tcl 4-391] The following IPs are missing output products for Synthesis target. These output products could be required for synthesis, please generate the output products using the generate_target or synth_ip command before running synth_design. WARNING: [Vivado_Tcl 4-391] The following IPs are missing output products for Implementation target. These output products could be required for synthesis, please generate the output products using the generate_target or synth_ip command before running synth_design. WARNING: [IP_Flow 19-2162] IP 'xge_pcs_pma' is locked: ERROR: [Synth 8-439] module 'xge_pcs_pma' not found ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command. ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command. ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command. ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command. ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command. ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command. CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/uhd/fpga/usrp3/top/x400/build-ip/xczu28drffvg1517-1e/xge_pcs_pma/xge_pcs_pma.xml' CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/uhd/fpga/usrp3/top/x400/build-ip/xczu28drffvg1517-1e/xge_pcs_pma/xge_pcs_pma.xml' CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/uhd/fpga/usrp3/top/x400/build-ip/xczu28drffvg1517-1e/xge_pcs_pma/xge_pcs_pma.xml' CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/uhd/fpga/usrp3/top/x400/build-ip/xczu28drffvg1517-1e/xge_pcs_pma/xge_pcs_pma.xml' CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/uhd/fpga/usrp3/top/x400/build-ip/xczu28drffvg1517-1e/xge_pcs_pma/xge_pcs_pma.xml' ERROR: [Vivado 12-398] No designs are open ERROR: [Common 17-69] Command failed: * IP definition '10G/25G Ethernet Subsystem (3.0)' for IP 'xge_pcs_pma' (customized with software release 2019.1.1) has a different revision in the IP Catalog. [00:00:23] Current task: Synthesis +++ Current Phase: Starting [00:00:23] Current task: Synthesis +++ Current Phase: Finished [00:00:23] Process terminated. Status: Failure ======================================================== Warnings: 4 Critical Warnings: 7 Errors: 10 BUILDER: Releasing IP location: /uhd/fpga/usrp3/top/x400/build-ip/xczu28drffvg1517-1e/xge_pcs_pma make[5]: *** [/uhd/fpga/usrp3/top/x400/ip/xge_pcs_pma/Makefile.inc:43: /uhd/fpga/usrp3/top/x400/build-ip/xczu28drffvg1517-1e/xge_pcs_pma/xge_pcs_pma.xci.out] Error 1 make[4]: *** [Makefile:129: X410_XG_100] Error 2 Built target x410_rfnoc_image_core

Hi, What did you run to get this error? Which version of the UHD repo are you using? Building the FPGA requires a Vivado license, but all of the IP is included with Vivado. Assuming you have a working Vivado license, please ensure you have the correct version of Vivado installed for the version of the FPGA you are building. The error message you received seems to suggest the version of Vivado you have installed doesn't match the version the IP is expecting: ERROR: [Common 17-69] Command failed: * IP definition '10G/25G Ethernet Subsystem (3.0)' for IP 'xge_pcs_pma' (customized with software release 2019.1.1) has a different revision in the IP Catalog. If the version of the IP that's included in your Vivado installation doesn't match the version of the IP that the UHD repo uses then Vivado will "lock" the IP, causing the build to fail. Thanks, Wade On Sun, Jul 23, 2023 at 12:48 AM Aerman TUERXUN < armantursun@g.ecc.u-tokyo.ac.jp> wrote: > Hi USRP users, > > I am trying to build a gain block on USRP X410. > When I tried to build bitstream for X410_XG_100, I got the following > errors. > Seems some IP is locked for USRP X410. > Does that mean I need to purchase the IPs for building bitstream? > It's odd to me that we still need to buy specific IPs to build bitsstream > with RFNoC. > How can I build a bitstream for X410? > Thanks in advance. > > Environment successfully initialized. > BUILDER: Checking tools... > * GNU bash, version 5.0.17(1)-release (x86_64-pc-linux-gnu) > * Python 3.8.10 > * Vivado v2019.1 (64-bit) > ======================================================== > BUILDER: Building IP xge_pcs_pma > ======================================================== > BUILDER: Staging IP in build directory... > BUILDER: Reserving IP location: > /uhd/fpga/usrp3/top/x400/build-ip/xczu28drffvg1517-1e/xge_pcs_pma > BUILDER: Retargeting IP to part zynquplusRFSOC/xczu28dr/ffvg1517/-1/e... > BUILDER: Building IP... > [00:00:00] Executing command: vivado -mode batch -source > /uhd/fpga/usrp3/tools/scripts/viv_generate_ip.tcl -log xge_pcs_pma.log > -nojournal > WARNING: [IP_Flow 19-2162] IP 'xge_pcs_pma' is locked: > CRITICAL WARNING: [filemgmt 20-1366] Unable to reset target(s) for the > following file is locked: > /uhd/fpga/usrp3/top/x400/build-ip/xczu28drffvg1517-1e/xge_pcs_pma/xge_pcs_pma.xci > CRITICAL WARNING: [filemgmt 20-1365] Unable to generate target(s) for the > following file is locked: > /uhd/fpga/usrp3/top/x400/build-ip/xczu28drffvg1517-1e/xge_pcs_pma/xge_pcs_pma.xci > [00:00:09] Current task: Initialization +++ Current Phase: Starting > [00:00:09] Current task: Initialization +++ Current Phase: Finished > [00:00:09] Executing Tcl: synth_design -top xge_pcs_pma -part > xczu28dr-ffvg1517-1-e -mode out_of_context > [00:00:09] Starting Synthesis Command > WARNING: [Vivado_Tcl 4-391] The following IPs are missing output products > for Synthesis target. These output products could be required for > synthesis, please generate the output products using the generate_target or > synth_ip command before running synth_design. > WARNING: [Vivado_Tcl 4-391] The following IPs are missing output products > for Implementation target. These output products could be required for > synthesis, please generate the output products using the generate_target or > synth_ip command before running synth_design. > WARNING: [IP_Flow 19-2162] IP 'xge_pcs_pma' is locked: > ERROR: [Synth 8-439] module 'xge_pcs_pma' not found > ERROR: [Common 17-69] Command failed: Synthesis failed - please see the > console or run log file for details > ERROR: [Common 17-53] User Exception: No open design. Please open an > elaborated, synthesized or implemented design before executing this command. > ERROR: [Common 17-53] User Exception: No open design. Please open an > elaborated, synthesized or implemented design before executing this command. > ERROR: [Common 17-53] User Exception: No open design. Please open an > elaborated, synthesized or implemented design before executing this command. > ERROR: [Common 17-53] User Exception: No open design. Please open an > elaborated, synthesized or implemented design before executing this command. > ERROR: [Common 17-53] User Exception: No open design. Please open an > elaborated, synthesized or implemented design before executing this command. > ERROR: [Common 17-53] User Exception: No open design. Please open an > elaborated, synthesized or implemented design before executing this command. > CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file > '/uhd/fpga/usrp3/top/x400/build-ip/xczu28drffvg1517-1e/xge_pcs_pma/xge_pcs_pma.xml' > CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file > '/uhd/fpga/usrp3/top/x400/build-ip/xczu28drffvg1517-1e/xge_pcs_pma/xge_pcs_pma.xml' > CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file > '/uhd/fpga/usrp3/top/x400/build-ip/xczu28drffvg1517-1e/xge_pcs_pma/xge_pcs_pma.xml' > CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file > '/uhd/fpga/usrp3/top/x400/build-ip/xczu28drffvg1517-1e/xge_pcs_pma/xge_pcs_pma.xml' > CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file > '/uhd/fpga/usrp3/top/x400/build-ip/xczu28drffvg1517-1e/xge_pcs_pma/xge_pcs_pma.xml' > ERROR: [Vivado 12-398] No designs are open > ERROR: [Common 17-69] Command failed: * IP definition '10G/25G Ethernet > Subsystem (3.0)' for IP 'xge_pcs_pma' (customized with software release > 2019.1.1) has a different revision in the IP Catalog. > [00:00:23] Current task: Synthesis +++ Current Phase: Starting > [00:00:23] Current task: Synthesis +++ Current Phase: Finished > [00:00:23] Process terminated. Status: Failure > > ======================================================== > Warnings: 4 > Critical Warnings: 7 > Errors: 10 > > BUILDER: Releasing IP location: > /uhd/fpga/usrp3/top/x400/build-ip/xczu28drffvg1517-1e/xge_pcs_pma > make[5]: *** [/uhd/fpga/usrp3/top/x400/ip/xge_pcs_pma/Makefile.inc:43: > /uhd/fpga/usrp3/top/x400/build-ip/xczu28drffvg1517-1e/xge_pcs_pma/xge_pcs_pma.xci.out] > Error 1 > make[4]: *** [Makefile:129: X410_XG_100] Error 2 > Built target x410_rfnoc_image_core > _______________________________________________ > USRP-users mailing list -- usrp-users@lists.ettus.com > To unsubscribe send an email to usrp-users-leave@lists.ettus.com >

Hi Wade, Thank you for your reply. I got this error when I ran "make x410_100_rfnoc_image_core". And I am using UHD-4.2 and Vivado 2019.1.1. How can I check the required IP version of UHD? Is there any way to know whether I should upgrade or downgrade the Vivado version? Also, I am holding a University License of Vivado, is it possible that IP is not available for my license? Thanks. Regards, Arman On Tue, Jul 25, 2023 at 7:04 AM Wade Fife <wade.fife@ettus.com> wrote: > Hi, > > What did you run to get this error? Which version of the UHD repo are you > using? > > Building the FPGA requires a Vivado license, but all of the IP is included > with Vivado. Assuming you have a working Vivado license, please ensure you > have the correct version of Vivado installed for the version of the FPGA > you are building. The error message you received seems to suggest the > version of Vivado you have installed doesn't match the version the IP is > expecting: > > ERROR: [Common 17-69] Command failed: * IP definition '10G/25G Ethernet > Subsystem (3.0)' for IP 'xge_pcs_pma' (customized with software release > 2019.1.1) has a different revision in the IP Catalog. > > If the version of the IP that's included in your Vivado installation > doesn't match the version of the IP that the UHD repo uses then Vivado will > "lock" the IP, causing the build to fail. > > Thanks, > > Wade > > On Sun, Jul 23, 2023 at 12:48 AM Aerman TUERXUN < > armantursun@g.ecc.u-tokyo.ac.jp> wrote: > >> Hi USRP users, >> >> I am trying to build a gain block on USRP X410. >> When I tried to build bitstream for X410_XG_100, I got the following >> errors. >> Seems some IP is locked for USRP X410. >> Does that mean I need to purchase the IPs for building bitstream? >> It's odd to me that we still need to buy specific IPs to build bitsstream >> with RFNoC. >> How can I build a bitstream for X410? >> Thanks in advance. >> >> Environment successfully initialized. >> BUILDER: Checking tools... >> * GNU bash, version 5.0.17(1)-release (x86_64-pc-linux-gnu) >> * Python 3.8.10 >> * Vivado v2019.1 (64-bit) >> ======================================================== >> BUILDER: Building IP xge_pcs_pma >> ======================================================== >> BUILDER: Staging IP in build directory... >> BUILDER: Reserving IP location: >> /uhd/fpga/usrp3/top/x400/build-ip/xczu28drffvg1517-1e/xge_pcs_pma >> BUILDER: Retargeting IP to part zynquplusRFSOC/xczu28dr/ffvg1517/-1/e... >> BUILDER: Building IP... >> [00:00:00] Executing command: vivado -mode batch -source >> /uhd/fpga/usrp3/tools/scripts/viv_generate_ip.tcl -log xge_pcs_pma.log >> -nojournal >> WARNING: [IP_Flow 19-2162] IP 'xge_pcs_pma' is locked: >> CRITICAL WARNING: [filemgmt 20-1366] Unable to reset target(s) for the >> following file is locked: >> /uhd/fpga/usrp3/top/x400/build-ip/xczu28drffvg1517-1e/xge_pcs_pma/xge_pcs_pma.xci >> CRITICAL WARNING: [filemgmt 20-1365] Unable to generate target(s) for the >> following file is locked: >> /uhd/fpga/usrp3/top/x400/build-ip/xczu28drffvg1517-1e/xge_pcs_pma/xge_pcs_pma.xci >> [00:00:09] Current task: Initialization +++ Current Phase: Starting >> [00:00:09] Current task: Initialization +++ Current Phase: Finished >> [00:00:09] Executing Tcl: synth_design -top xge_pcs_pma -part >> xczu28dr-ffvg1517-1-e -mode out_of_context >> [00:00:09] Starting Synthesis Command >> WARNING: [Vivado_Tcl 4-391] The following IPs are missing output products >> for Synthesis target. These output products could be required for >> synthesis, please generate the output products using the generate_target or >> synth_ip command before running synth_design. >> WARNING: [Vivado_Tcl 4-391] The following IPs are missing output products >> for Implementation target. These output products could be required for >> synthesis, please generate the output products using the generate_target or >> synth_ip command before running synth_design. >> WARNING: [IP_Flow 19-2162] IP 'xge_pcs_pma' is locked: >> ERROR: [Synth 8-439] module 'xge_pcs_pma' not found >> ERROR: [Common 17-69] Command failed: Synthesis failed - please see the >> console or run log file for details >> ERROR: [Common 17-53] User Exception: No open design. Please open an >> elaborated, synthesized or implemented design before executing this command. >> ERROR: [Common 17-53] User Exception: No open design. Please open an >> elaborated, synthesized or implemented design before executing this command. >> ERROR: [Common 17-53] User Exception: No open design. Please open an >> elaborated, synthesized or implemented design before executing this command. >> ERROR: [Common 17-53] User Exception: No open design. Please open an >> elaborated, synthesized or implemented design before executing this command. >> ERROR: [Common 17-53] User Exception: No open design. Please open an >> elaborated, synthesized or implemented design before executing this command. >> ERROR: [Common 17-53] User Exception: No open design. Please open an >> elaborated, synthesized or implemented design before executing this command. >> CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file >> '/uhd/fpga/usrp3/top/x400/build-ip/xczu28drffvg1517-1e/xge_pcs_pma/xge_pcs_pma.xml' >> CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file >> '/uhd/fpga/usrp3/top/x400/build-ip/xczu28drffvg1517-1e/xge_pcs_pma/xge_pcs_pma.xml' >> CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file >> '/uhd/fpga/usrp3/top/x400/build-ip/xczu28drffvg1517-1e/xge_pcs_pma/xge_pcs_pma.xml' >> CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file >> '/uhd/fpga/usrp3/top/x400/build-ip/xczu28drffvg1517-1e/xge_pcs_pma/xge_pcs_pma.xml' >> CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file >> '/uhd/fpga/usrp3/top/x400/build-ip/xczu28drffvg1517-1e/xge_pcs_pma/xge_pcs_pma.xml' >> ERROR: [Vivado 12-398] No designs are open >> ERROR: [Common 17-69] Command failed: * IP definition '10G/25G Ethernet >> Subsystem (3.0)' for IP 'xge_pcs_pma' (customized with software release >> 2019.1.1) has a different revision in the IP Catalog. >> [00:00:23] Current task: Synthesis +++ Current Phase: Starting >> [00:00:23] Current task: Synthesis +++ Current Phase: Finished >> [00:00:23] Process terminated. Status: Failure >> >> ======================================================== >> Warnings: 4 >> Critical Warnings: 7 >> Errors: 10 >> >> BUILDER: Releasing IP location: >> /uhd/fpga/usrp3/top/x400/build-ip/xczu28drffvg1517-1e/xge_pcs_pma >> make[5]: *** [/uhd/fpga/usrp3/top/x400/ip/xge_pcs_pma/Makefile.inc:43: >> /uhd/fpga/usrp3/top/x400/build-ip/xczu28drffvg1517-1e/xge_pcs_pma/xge_pcs_pma.xci.out] >> Error 1 >> make[4]: *** [Makefile:129: X410_XG_100] Error 2 >> Built target x410_rfnoc_image_core >> _______________________________________________ >> USRP-users mailing list -- usrp-users@lists.ettus.com >> To unsubscribe send an email to usrp-users-leave@lists.ettus.com >> >

The exact Vivado version required for UHD 4.2 is 2019.1.1_AR73068. Make sure you have Vivado patch AR 73068 installed: https://github.com/EttusResearch/uhd/blob/UHD-4.2/fpga/usrp3/top/x400/setupenv.sh#L9 Running `source setupenv.sh` should check the Vivado version and provide an error message if the version is not correct. In your case, it failed on xge_pcs_pma which needs to be version 3.0 of xxv_ethernet: https://github.com/EttusResearch/uhd/blob/UHD-4.2/fpga/usrp3/top/x400/ip/xge_pcs_pma/xge_pcs_pma.xci#L10 In general, the first step is to make sure you have the right Vivado version and patches installed. Then try building an unmodified FPGA to make sure things are working: cd uhd/fpga/usrp3/top/x400 source setupenv.sh make X410_XG_100 Once that's working, then try building your custom FPGA again. Wade On Tue, Jul 25, 2023 at 1:08 AM Aerman TUERXUN < armantursun@g.ecc.u-tokyo.ac.jp> wrote: > Hi Wade, > > Thank you for your reply. > I got this error when I ran "make x410_100_rfnoc_image_core". > And I am using UHD-4.2 and Vivado 2019.1.1. > > How can I check the required IP version of UHD? Is there any way to know > whether I should upgrade or downgrade the Vivado version? > Also, I am holding a University License of Vivado, is it possible that IP > is not available for my license? > Thanks. > > Regards, > Arman > > > On Tue, Jul 25, 2023 at 7:04 AM Wade Fife <wade.fife@ettus.com> wrote: > >> Hi, >> >> What did you run to get this error? Which version of the UHD repo are you >> using? >> >> Building the FPGA requires a Vivado license, but all of the IP is >> included with Vivado. Assuming you have a working Vivado license, please >> ensure you have the correct version of Vivado installed for the version of >> the FPGA you are building. The error message you received seems to suggest >> the version of Vivado you have installed doesn't match the version the IP >> is expecting: >> >> ERROR: [Common 17-69] Command failed: * IP definition '10G/25G Ethernet >> Subsystem (3.0)' for IP 'xge_pcs_pma' (customized with software release >> 2019.1.1) has a different revision in the IP Catalog. >> >> If the version of the IP that's included in your Vivado installation >> doesn't match the version of the IP that the UHD repo uses then Vivado will >> "lock" the IP, causing the build to fail. >> >> Thanks, >> >> Wade >> >> On Sun, Jul 23, 2023 at 12:48 AM Aerman TUERXUN < >> armantursun@g.ecc.u-tokyo.ac.jp> wrote: >> >>> Hi USRP users, >>> >>> I am trying to build a gain block on USRP X410. >>> When I tried to build bitstream for X410_XG_100, I got the following >>> errors. >>> Seems some IP is locked for USRP X410. >>> Does that mean I need to purchase the IPs for building bitstream? >>> It's odd to me that we still need to buy specific IPs to build >>> bitsstream with RFNoC. >>> How can I build a bitstream for X410? >>> Thanks in advance. >>> >>> Environment successfully initialized. >>> BUILDER: Checking tools... >>> * GNU bash, version 5.0.17(1)-release (x86_64-pc-linux-gnu) >>> * Python 3.8.10 >>> * Vivado v2019.1 (64-bit) >>> ======================================================== >>> BUILDER: Building IP xge_pcs_pma >>> ======================================================== >>> BUILDER: Staging IP in build directory... >>> BUILDER: Reserving IP location: >>> /uhd/fpga/usrp3/top/x400/build-ip/xczu28drffvg1517-1e/xge_pcs_pma >>> BUILDER: Retargeting IP to part zynquplusRFSOC/xczu28dr/ffvg1517/-1/e... >>> BUILDER: Building IP... >>> [00:00:00] Executing command: vivado -mode batch -source >>> /uhd/fpga/usrp3/tools/scripts/viv_generate_ip.tcl -log xge_pcs_pma.log >>> -nojournal >>> WARNING: [IP_Flow 19-2162] IP 'xge_pcs_pma' is locked: >>> CRITICAL WARNING: [filemgmt 20-1366] Unable to reset target(s) for the >>> following file is locked: >>> /uhd/fpga/usrp3/top/x400/build-ip/xczu28drffvg1517-1e/xge_pcs_pma/xge_pcs_pma.xci >>> CRITICAL WARNING: [filemgmt 20-1365] Unable to generate target(s) for >>> the following file is locked: >>> /uhd/fpga/usrp3/top/x400/build-ip/xczu28drffvg1517-1e/xge_pcs_pma/xge_pcs_pma.xci >>> [00:00:09] Current task: Initialization +++ Current Phase: Starting >>> [00:00:09] Current task: Initialization +++ Current Phase: Finished >>> [00:00:09] Executing Tcl: synth_design -top xge_pcs_pma -part >>> xczu28dr-ffvg1517-1-e -mode out_of_context >>> [00:00:09] Starting Synthesis Command >>> WARNING: [Vivado_Tcl 4-391] The following IPs are missing output >>> products for Synthesis target. These output products could be required for >>> synthesis, please generate the output products using the generate_target or >>> synth_ip command before running synth_design. >>> WARNING: [Vivado_Tcl 4-391] The following IPs are missing output >>> products for Implementation target. These output products could be required >>> for synthesis, please generate the output products using the >>> generate_target or synth_ip command before running synth_design. >>> WARNING: [IP_Flow 19-2162] IP 'xge_pcs_pma' is locked: >>> ERROR: [Synth 8-439] module 'xge_pcs_pma' not found >>> ERROR: [Common 17-69] Command failed: Synthesis failed - please see the >>> console or run log file for details >>> ERROR: [Common 17-53] User Exception: No open design. Please open an >>> elaborated, synthesized or implemented design before executing this command. >>> ERROR: [Common 17-53] User Exception: No open design. Please open an >>> elaborated, synthesized or implemented design before executing this command. >>> ERROR: [Common 17-53] User Exception: No open design. Please open an >>> elaborated, synthesized or implemented design before executing this command. >>> ERROR: [Common 17-53] User Exception: No open design. Please open an >>> elaborated, synthesized or implemented design before executing this command. >>> ERROR: [Common 17-53] User Exception: No open design. Please open an >>> elaborated, synthesized or implemented design before executing this command. >>> ERROR: [Common 17-53] User Exception: No open design. Please open an >>> elaborated, synthesized or implemented design before executing this command. >>> CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file >>> '/uhd/fpga/usrp3/top/x400/build-ip/xczu28drffvg1517-1e/xge_pcs_pma/xge_pcs_pma.xml' >>> CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file >>> '/uhd/fpga/usrp3/top/x400/build-ip/xczu28drffvg1517-1e/xge_pcs_pma/xge_pcs_pma.xml' >>> CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file >>> '/uhd/fpga/usrp3/top/x400/build-ip/xczu28drffvg1517-1e/xge_pcs_pma/xge_pcs_pma.xml' >>> CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file >>> '/uhd/fpga/usrp3/top/x400/build-ip/xczu28drffvg1517-1e/xge_pcs_pma/xge_pcs_pma.xml' >>> CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file >>> '/uhd/fpga/usrp3/top/x400/build-ip/xczu28drffvg1517-1e/xge_pcs_pma/xge_pcs_pma.xml' >>> ERROR: [Vivado 12-398] No designs are open >>> ERROR: [Common 17-69] Command failed: * IP definition '10G/25G Ethernet >>> Subsystem (3.0)' for IP 'xge_pcs_pma' (customized with software release >>> 2019.1.1) has a different revision in the IP Catalog. >>> [00:00:23] Current task: Synthesis +++ Current Phase: Starting >>> [00:00:23] Current task: Synthesis +++ Current Phase: Finished >>> [00:00:23] Process terminated. Status: Failure >>> >>> ======================================================== >>> Warnings: 4 >>> Critical Warnings: 7 >>> Errors: 10 >>> >>> BUILDER: Releasing IP location: >>> /uhd/fpga/usrp3/top/x400/build-ip/xczu28drffvg1517-1e/xge_pcs_pma >>> make[5]: *** [/uhd/fpga/usrp3/top/x400/ip/xge_pcs_pma/Makefile.inc:43: >>> /uhd/fpga/usrp3/top/x400/build-ip/xczu28drffvg1517-1e/xge_pcs_pma/xge_pcs_pma.xci.out] >>> Error 1 >>> make[4]: *** [Makefile:129: X410_XG_100] Error 2 >>> Built target x410_rfnoc_image_core >>> _______________________________________________ >>> USRP-users mailing list -- usrp-users@lists.ettus.com >>> To unsubscribe send an email to usrp-users-leave@lists.ettus.com >>> >>