Hi All, I am currently using two N210/SBX units. Both have 10MHz and 1PPS references. I have implemented timed commands but I am still getting random phase offsets across the devices. I am trying to locate in the N210 FPGA source code, where the LE signal of the ADF4350 PLL is generated. Can anyone point me in the right place ? I am trying to understand how this signal is generated as I failed to measure the signals from both N210/SBX units on a scope. I know the ADF4350 PLL has a phase sync feature which resets to a consistent phase offset from the reference input, but I need to make sure after a frequency tune the LE signal is generated at the same time for both N210/SBX units so the dividers start together. Any help locating this code would be great. Thanks, Nigel

Hi Nigel, I'll explain what I did to figure such things out: on the SBX, U23's LE pin 3 (on page 3) goes to the RX daughterboard connector pin 3 (on page4). On the N210's schematic, p. 3, pin 35 of the RX dboard connector is the signal "SEN_RX_DB", which, on page 11, is connected to the FPGA's pin "IO_L02P_3", B2. Now, knowing "B2", we can go to the ucf file of the N210 [1], where it says: NET "SEN_RX_DB" LOC = "B2" ; so we now know what to "git grep" for :) in fpga-src/usrp2 [2]. We see that top/N2x0/u2plus.v contains that string on lines 79 and especiall 441, where it is an output of the u2plus_core module. Now, a bit of grepping later, we know that u2plus_core is in the .v of the same name, where sen_rx_db (which is the signal name inside the module) is just the output of a simple_spi_core instance. That means that the host just sends the SPI commands to the FPGA, where they get electrically executed. Does that answer your question? Best regards, Marcus [1] fpga-src/usrp2/top/N2x0/something.ucf [2] In fact, I use "ack", instead of "git grep" for the shorter command and nice file type filters: "ack --verilog SEN_RX_DB" On 21.02.2016 22:14, Nigel Steed via USRP-users wrote: > > Hi All, > > > > I am currently using two N210/SBX units. Both have 10MHz and 1PPS > references. I have implemented timed commands but I am still getting > random phase offsets across the devices. > > > > I am trying to locate in the N210 FPGA source code, where the LE > signal of the ADF4350 PLL is generated. Can anyone point me in the > right place ? > > > > I am trying to understand how this signal is generated as I failed to > measure the signals from both N210/SBX units on a scope. I know the > ADF4350 PLL has a phase sync feature which resets to a consistent > phase offset from the reference input, but I need to make sure after a > frequency tune the LE signal is generated at the same time for both > N210/SBX units so the dividers start together. > > > > Any help locating this code would be great. > > > > Thanks, > > > > Nigel > > > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com

Hi Nigel, At a high level, the LE on both devices will happen at the same time if the devices are properly time synchronized using a common PPS and 10 MHz reference and the tuning is done using timed commands. In the FPGA, the actual assertion of the LE is done by the simple_spi_core module, but the timing is controlled by the vita_rx/tx_control module. How are you measuring phase offset? Can you share any code or a flowgraph? Regards, Michael On Sun, Feb 21, 2016 at 1:51 PM, Marcus Müller <usrp-users@lists.ettus.com> wrote: > Hi Nigel, > > I'll explain what I did to figure such things out: > on the SBX, U23's LE pin 3 (on page 3) goes to the RX daughterboard > connector pin 3 (on page4). > On the N210's schematic, p. 3, pin 35 of the RX dboard connector is the > signal "SEN_RX_DB", which, on page 11, is connected to the FPGA's pin > "IO_L02P_3", B2. > Now, knowing "B2", we can go to the ucf file of the N210 [1], where it > says: > > NET "SEN_RX_DB" LOC = "B2" ; > > so we now know what to "git grep" for :) in fpga-src/usrp2 [2]. We see > that top/N2x0/u2plus.v contains that string on lines 79 and especiall 441, > where it is an output of the u2plus_core module. Now, a bit of grepping > later, we know that u2plus_core is in the .v of the same name, where > sen_rx_db (which is the signal name inside the module) is just the output > of a simple_spi_core instance. > > That means that the host just sends the SPI commands to the FPGA, where > they get electrically executed. > > Does that answer your question? > > Best regards, > Marcus > > > > > [1] fpga-src/usrp2/top/N2x0/something.ucf > [2] In fact, I use "ack", instead of "git grep" for the shorter command > and nice file type filters: "ack --verilog SEN_RX_DB" > > > On 21.02.2016 22:14, Nigel Steed via USRP-users wrote: > > Hi All, > > > > I am currently using two N210/SBX units. Both have 10MHz and 1PPS > references. I have implemented timed commands but I am still getting random > phase offsets across the devices. > > > > I am trying to locate in the N210 FPGA source code, where the LE signal of > the ADF4350 PLL is generated. Can anyone point me in the right place ? > > > > I am trying to understand how this signal is generated as I failed to > measure the signals from both N210/SBX units on a scope. I know the ADF4350 > PLL has a phase sync feature which resets to a consistent phase offset from > the reference input, but I need to make sure after a frequency tune the LE > signal is generated at the same time for both N210/SBX units so the > dividers start together. > > > > Any help locating this code would be great. > > > > Thanks, > > > > Nigel > > > _______________________________________________ > USRP-users mailing listUSRP-users@lists.ettus.comhttp://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > > > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > >