If you have a clean input signal, a Schmitt trigger doesn't solve any
problems.  It does help if you have a slowly rising signal such that noise
might be significant while the signal is near threshold.  A 10 MHz sine wave
is slow relative to AC logic.

Since we were recently speaking of LPROs, their user manual has a section on
how to convert 10 MHz sine waves into TTL signals.  None of their suggestions
used Schmitt triggers.

This feels like the sort of thing that should have been hashed out here by
now.  Is it time to start a FAQ?

My straw man would be to capacitive couple into a 74AC00 that's biased
halfway between VCC and GND.  That's clean and simple.  A transformer would
break ground loops.  A differential input chip might reduce jitter from noise
on the power supply.

Dividing by 10 is simple.  Doing it with symmetrical output takes a bit
more/different logic than comes prepackaged in a single DIP, or at least not
any that I'm familiar with.

Plan A would use a 4 bit loadable counter and load it with 3 when it reads 12
so the top bit would be off for 5 cycles, 3 through 7, then on for 5 cycles,
8 through 12.  That's reasonable to implement in old TTL DIPs.  12 is easy to
decode, just a 2 input gate since states 13-15 won't happen.  74xx163 and
74xx00

Plan B would be to use a PAL or CPLD.  I don't know of any that are available
in DIP, have free design software, and are easy to program without a fancy
programmer.  There could easily be something I don't know about.  I know that
Xilinx CPLDs have free software (WebPACK) but they don't come in DIP.  A
friend has written software to program them, but he's a wizard so I don't
know if mortals could do it.  WebPACK may do the programming if you have a
gizmo.  One is available at a reasonable price from Digilent.

This technology is too handy.  There is probably some hobbyist friendly setup
out there.  You may have to build a programmer.

--
These are my opinions, not necessarily my employer's.  I hate spam.

Hal Murray wrote:

The TADD-2 uses an input circuit published by Wenzel in their "Waveform
Conversion" document at http://www.wenzel.com/documents/waveform.html.

I haven't measured its standalone jitter, but its input sensitivity is
great --  it will reliably trigger a CMOS gate from an input at least
down to -10 dBm, maybe lower (I don't recall the exact limits I found
when I tested).  If you build this, note one thing -- with the 100 ohm
emitter resistor specified, the square wave output is more like 6V than
5V p-p.  I use 120 ohms instead to get a 5 volt output.

While the Wenzel circuit requires a modest handful of discrete
components, I think it's the most useful solution by a pretty clear
margin for our typical requirement of driving a single-ended logic gate
from an HF source.

John

Hal

Hal Murray wrote:

A large resistor connected between the input and output would
accommodate threshold variations better.
Even better would be a feedback loop that adjusts the input bias point
to maintain the output duty cycle at 50%.

However if you use such a threshold adjustment lop with a Schmitt
trigger it will oscillate at a low frequency when there is no input signal.

A simple low Q tuned circuit can be used to boost the signal amplitude
at the gate input if necessary.

The venerable Johnson decade counter such as a 4017 or 74HC4017 does
this in a DIP package.

Digilent have suitable Xilinx  CPLDs mounted on DIP compatible daughter
boards.
The CPLDs are programmed via the JTAG port.
Suitable JTAG programming cables are readily availble.

Bruce

John Ackermann N8UR wrote:

John

One could also use a PECL to TTL level translator.

JPL have used ECL dividers throughout to produce 10MHz, 1MHz and 100KHz
outputs from the 100MHz signal derived from a Hydrogen maser:
http://tmo.jpl.nasa.gov/progress_report2/42-30/30I.PDF

Where TTL outputs are required an ECL to TTl translator followed by a
discrete amplifier to drive TTL levels in a 50 ohm load was used.

Bruce

Or you can build one to use the LPT port of your PC using just a 74HC244.

Luis Cupido.
ct1dmk.

Luis Cupido wrote:

Luis

Using a 74HC244 may be somewhat  problematic with CPLDs that don't have
5V tolerant inputs.
Even when using a device with 5V tolerant inputs a 74HCT244 may be more
suitable for translating LVCMOS logic level outputs from the CPLD.

Bruce

Bruce,

There is a trick...
That JTAG interface made with a 74HC244 is
powered from the target board,
If the target board runs at 5v so it will work
at 5v. No doubts here...

But if the target runs at 3v3 the 74HC244 gets powered
at 3v3 (and it works fine, no need for the target
device to be tolerant to anything, it gets within
whatever VDD it uses...)
and the 74HC244 seems to be tolerant to whatever comes
out of the PC LPT port, but has a few series resistors though.

Amazingly it even works at 2v5 !

The byteblasterMV from Altera is just like that and it
works great, and programs from the small CPLDs up to
most of the FPGA's (except for some more recent ones that
require someting else... but is not a voltage issue).

I'm running one for ages now with zero issues in both
5v chips and 3v3 chips.

I even made a byteblasterII (to use on the more recent FPGA's)
with the same 74HC244 (adding a few bits to the
original byteblasterMV for the additional features required)
and it works just fine even with Cyclone devices.

Luis Cupido.
ct1dmk.

Bruce Griffiths wrote:

Luis

Luis Cupido wrote:

The current flowing in the input protection diodes of the 74HC244 needs
to be limited to protect both the 74NC244 and the driving device in the PC.
The potential increased jitter when current flows in the protection
diodes isn't significant here.

Since 74HC244 is specified to work with power supply range of 2V to 6V
that isn't too surprising as long as the ~ 4x increase in propagation
delay when going from a 5V supply to a 2.5V supply is acceptable.
With a power supply below 2.5V the 74HC244 output swing wont meet the
upper TTL threshold of the parallel port input,

Bruce

Hal Murray skrev:

Schmitt triggers seems to be misunderstood by many. They do NOT
magically solve all issues with noise in the correct way. It seems
strange that one actually has to say that, but it seems to be a widely
accepted fact that if one uses a schmitt trigger one is doing the right
thing. The answer is really maybe, it depends. There are many things
where it is just what should be used. For trigger signals where jitter
may be of concern you can do better. If the signal first hits a Schmitt
trigger, then the noise will modulate the trigger point with the
achieved slope at that stage, and no further processing will improve on
that but a full sufficiently narrow bandwidth PLL. If instead the slope
was linearly amplified to increase the slew rate at the desired trigger
voltage, then a much lower trigger jitter can be achived. Anyone
following the conversations of Bruce and myself should recognise this as
a reoccurring thing.

Bruce already has a bit of useful information, TvB certainly has, along
side of several other good members. Besides, folks here is very helpful
and eager to help a fellow time-nut. We also have archives.

You can use self-biasing unbuffered CMOS inverters such as 4069UB as a
first stage amplifier and then use a few more in sequence to achieve
further gain. This trick have been used before and while certainly not
optimum it could be a useful little trick for simple single-chip
solutions where no major performance is expected. Hmm... I should
actually measure that one...

The problem with the '90 is really that the output is not properly
synchronised. A half '74 solves that problem. The '90 is doing the
needed state-change, the '74 does the needed clock alignment.

The parallel port adapter is soooo easy. Infact you will find the
schematic of Xilinx dongle on their web. The JTAG variant is however not
so simple...

Cheers,
Magnus

Bruce and Luis,

One chip that works very well for TDI/TMS/TCK translation from the printer
port into the cpld is the 74AHC125 with its VCC connected to the cpld's VCC.
This one can work with VCC as low as 2.0 V and is still 5 V tolerant on all
inputs. At least with 3.3 cplds it's output swing is high enough for TDO
back-translation. With 2.5 / 1.8 V cplds a separate TDO back-translation may
become necessary.

Best regards
Ulrich