Hi USRP users, I am currently developing an OOT RFNoC module. When I tried to build a custom image, it gave me errors as below. I checked the python path, and it seems fine. Is there anyone that has any idea of the reason for this? I am using n310 with uhd v4.2.0.0. (I checked with uhd4.0, and didn't encounter this problem). Thanks in advance. Best regards. Traceback (most recent call last): File "/usr/local/bin/rfnoc_image_builder", line 29, in <module> from uhd.imgbuilder import image_builder ModuleNotFoundError: No module named 'uhd' make[3]: *** [icores/CMakeFiles/n310_rfnoc_image_core.dir/build.make:57: icores/CMakeFiles/n310_rfnoc_image_core] Error 1 make[2]: *** [CMakeFiles/Makefile2:300: icores/CMakeFiles/n310_rfnoc_image_core.dir/all] Error 2 make[1]: *** [CMakeFiles/Makefile2:307: icores/CMakeFiles/n310_rfnoc_image_core.dir/rule] Error 2 make: *** [Makefile:203: n310_rfnoc_image_core] Error 2

I also checked the uhd installation logs. Why it couldn't find the uhd module? -- Up-to-date: /usr/local/lib/python3.8/site-packages/uhd -- Up-to-date: /usr/local/lib/python3.8/site-packages/uhd/imgbuilder -- Installing: /usr/local/lib/python3.8/site-packages/uhd/imgbuilder/yaml_utils.py -- Installing: /usr/local/lib/python3.8/site-packages/uhd/imgbuilder/__init__.py -- Up-to-date: /usr/local/lib/python3.8/site-packages/uhd/imgbuilder/templates -- Installing: /usr/local/lib/python3.8/site-packages/uhd/imgbuilder/templates/rfnoc_image_core.vh.mako -- Installing: /usr/local/lib/python3.8/site-packages/uhd/imgbuilder/templates/rfnoc_image_core.v.mako -- Up-to-date: /usr/local/lib/python3.8/site-packages/uhd/imgbuilder/templates/modules -- Installing: /usr/local/lib/python3.8/site-packages/uhd/imgbuilder/templates/modules/connect_io_ports.v.mako -- Installing: /usr/local/lib/python3.8/site-packages/uhd/imgbuilder/templates/modules/device_transport.v.mako -- Installing: /usr/local/lib/python3.8/site-packages/uhd/imgbuilder/templates/modules/ctrl_crossbar.v.mako -- Installing: /usr/local/lib/python3.8/site-packages/uhd/imgbuilder/templates/modules/device_io_ports.v.mako -- Installing: /usr/local/lib/python3.8/site-packages/uhd/imgbuilder/templates/modules/chdr_xb_sep_transport.v.mako -- Installing: /usr/local/lib/python3.8/site-packages/uhd/imgbuilder/templates/modules/rfnoc_block.v.mako -- Installing: /usr/local/lib/python3.8/site-packages/uhd/imgbuilder/templates/modules/drive_unused_ports.v.mako -- Installing: /usr/local/lib/python3.8/site-packages/uhd/imgbuilder/templates/modules/static_router.v.mako -- Installing: /usr/local/lib/python3.8/site-packages/uhd/imgbuilder/templates/modules/stream_endpoints.v.mako -- Installing: /usr/local/lib/python3.8/site-packages/uhd/imgbuilder/templates/modules/sep_xb_wires.v.mako -- Installing: /usr/local/lib/python3.8/site-packages/uhd/imgbuilder/templates/modules/connect_clk_domains.v.mako -- Installing: /usr/local/lib/python3.8/site-packages/uhd/imgbuilder/image_builder.py On Wed, Mar 1, 2023 at 11:52 AM AERMAN TUERXUN. < armantursun@g.ecc.u-tokyo.ac.jp> wrote: > Hi USRP users, > > I am currently developing an OOT RFNoC module. > When I tried to build a custom image, it gave me errors as below. > I checked the python path, and it seems fine. > Is there anyone that has any idea of the reason for this? > I am using n310 with uhd v4.2.0.0. > (I checked with uhd4.0, and didn't encounter this problem). > > Thanks in advance. > Best regards. > > Traceback (most recent call last): > File "/usr/local/bin/rfnoc_image_builder", line 29, in <module> > from uhd.imgbuilder import image_builder > ModuleNotFoundError: No module named 'uhd' > make[3]: *** [icores/CMakeFiles/n310_rfnoc_image_core.dir/build.make:57: > icores/CMakeFiles/n310_rfnoc_image_core] Error 1 > make[2]: *** [CMakeFiles/Makefile2:300: > icores/CMakeFiles/n310_rfnoc_image_core.dir/all] Error 2 > make[1]: *** [CMakeFiles/Makefile2:307: > icores/CMakeFiles/n310_rfnoc_image_core.dir/rule] Error 2 > make: *** [Makefile:203: n310_rfnoc_image_core] Error 2 > > >

 Hi USRP users,

 I am currently developing an OOT RFNoC module.
 When I tried to build a custom image, it gave me errors as below.
 I checked the python path, and it seems fine.
 Is there anyone that has any idea of the reason for this?
 I am using n310 with uhd v4.2.0.0.
 (I checked with uhd4.0, and didn't encounter this problem).

 Thanks in advance.
 Best regards.

 Traceback (most recent call last):
   File "/usr/local/bin/rfnoc_image_builder", line 29, in <module>
     from uhd.imgbuilder import image_builder
 ModuleNotFoundError: No module named 'uhd'
 make[3]: ***
 [icores/CMakeFiles/n310_rfnoc_image_core.dir/build.make:57:
 icores/CMakeFiles/n310_rfnoc_image_core] Error 1
 make[2]: *** [CMakeFiles/Makefile2:300:
 icores/CMakeFiles/n310_rfnoc_image_core.dir/all] Error 2
 make[1]: *** [CMakeFiles/Makefile2:307:
 icores/CMakeFiles/n310_rfnoc_image_core.dir/rule] Error 2
 make: *** [Makefile:203: n310_rfnoc_image_core] Error 2

On 28/02/2023 23:01, AERMAN TUERXUN. wrote: > I also checked the uhd installation logs. > Why it couldn't find the uhd module? > > -- Up-to-date: /usr/local/lib/python3.8/site-packages/uhd > -- Up-to-date: /usr/local/lib/python3.8/site-packages/uhd/imgbuilder > -- Installing: > /usr/local/lib/python3.8/site-packages/uhd/imgbuilder/yaml_utils.py > -- Installing: > /usr/local/lib/python3.8/site-packages/uhd/imgbuilder/__init__.py > -- Up-to-date: > /usr/local/lib/python3.8/site-packages/uhd/imgbuilder/templates > -- Installing: > /usr/local/lib/python3.8/site-packages/uhd/imgbuilder/templates/rfnoc_image_core.vh.mako > -- Installing: > /usr/local/lib/python3.8/site-packages/uhd/imgbuilder/templates/rfnoc_image_core.v.mako > -- Up-to-date: > /usr/local/lib/python3.8/site-packages/uhd/imgbuilder/templates/modules > -- Installing: > /usr/local/lib/python3.8/site-packages/uhd/imgbuilder/templates/modules/connect_io_ports.v.mako > -- Installing: > /usr/local/lib/python3.8/site-packages/uhd/imgbuilder/templates/modules/device_transport.v.mako > -- Installing: > /usr/local/lib/python3.8/site-packages/uhd/imgbuilder/templates/modules/ctrl_crossbar.v.mako > -- Installing: > /usr/local/lib/python3.8/site-packages/uhd/imgbuilder/templates/modules/device_io_ports.v.mako > -- Installing: > /usr/local/lib/python3.8/site-packages/uhd/imgbuilder/templates/modules/chdr_xb_sep_transport.v.mako > -- Installing: > /usr/local/lib/python3.8/site-packages/uhd/imgbuilder/templates/modules/rfnoc_block.v.mako > -- Installing: > /usr/local/lib/python3.8/site-packages/uhd/imgbuilder/templates/modules/drive_unused_ports.v.mako > -- Installing: > /usr/local/lib/python3.8/site-packages/uhd/imgbuilder/templates/modules/static_router.v.mako > -- Installing: > /usr/local/lib/python3.8/site-packages/uhd/imgbuilder/templates/modules/stream_endpoints.v.mako > -- Installing: > /usr/local/lib/python3.8/site-packages/uhd/imgbuilder/templates/modules/sep_xb_wires.v.mako > -- Installing: > /usr/local/lib/python3.8/site-packages/uhd/imgbuilder/templates/modules/connect_clk_domains.v.mako > -- Installing: > /usr/local/lib/python3.8/site-packages/uhd/imgbuilder/image_builder.py > > On Wed, Mar 1, 2023 at 11:52 AM AERMAN TUERXUN. > <armantursun@g.ecc.u-tokyo.ac.jp> wrote: > > Hi USRP users, > > I am currently developing an OOT RFNoC module. > When I tried to build a custom image, it gave me errors as below. > I checked the python path, and it seems fine. > Is there anyone that has any idea of the reason for this? > I am using n310 with uhd v4.2.0.0. > (I checked with uhd4.0, and didn't encounter this problem). > > Thanks in advance. > Best regards. > > Traceback (most recent call last): >   File "/usr/local/bin/rfnoc_image_builder", line 29, in <module> >     from uhd.imgbuilder import image_builder > ModuleNotFoundError: No module named 'uhd' > make[3]: *** > [icores/CMakeFiles/n310_rfnoc_image_core.dir/build.make:57: > icores/CMakeFiles/n310_rfnoc_image_core] Error 1 > make[2]: *** [CMakeFiles/Makefile2:300: > icores/CMakeFiles/n310_rfnoc_image_core.dir/all] Error 2 > make[1]: *** [CMakeFiles/Makefile2:307: > icores/CMakeFiles/n310_rfnoc_image_core.dir/rule] Error 2 > make: *** [Makefile:203: n310_rfnoc_image_core] Error 2 > > > > _______________________________________________ > USRP-users mailing list --usrp-users@lists.ettus.com > To unsubscribe send an email tousrp-users-leave@lists.ettus.com Maybe your ld.so.conf doesn't include /usr/local/lib, or you didn't "sudo ldconfig" after doing the install? What's in your PYTHONPATH?  Is that path actually *exported* or did you set it locally in your .bashrc (or equivalent). If you manually go into python and: import uhd What happens?

Hi Marcus, Thank you for your help. I set it in the .bashrc file before. I exported it and now it's working. Best regards On Wed, Mar 1, 2023 at 1:06 PM Marcus D. Leech <patchvonbraun@gmail.com> wrote: > On 28/02/2023 23:01, AERMAN TUERXUN. wrote: > > I also checked the uhd installation logs. > Why it couldn't find the uhd module? > > -- Up-to-date: /usr/local/lib/python3.8/site-packages/uhd > -- Up-to-date: /usr/local/lib/python3.8/site-packages/uhd/imgbuilder > -- Installing: > /usr/local/lib/python3.8/site-packages/uhd/imgbuilder/yaml_utils.py > -- Installing: > /usr/local/lib/python3.8/site-packages/uhd/imgbuilder/__init__.py > -- Up-to-date: > /usr/local/lib/python3.8/site-packages/uhd/imgbuilder/templates > -- Installing: > /usr/local/lib/python3.8/site-packages/uhd/imgbuilder/templates/rfnoc_image_core.vh.mako > -- Installing: > /usr/local/lib/python3.8/site-packages/uhd/imgbuilder/templates/rfnoc_image_core.v.mako > -- Up-to-date: > /usr/local/lib/python3.8/site-packages/uhd/imgbuilder/templates/modules > -- Installing: > /usr/local/lib/python3.8/site-packages/uhd/imgbuilder/templates/modules/connect_io_ports.v.mako > -- Installing: > /usr/local/lib/python3.8/site-packages/uhd/imgbuilder/templates/modules/device_transport.v.mako > -- Installing: > /usr/local/lib/python3.8/site-packages/uhd/imgbuilder/templates/modules/ctrl_crossbar.v.mako > -- Installing: > /usr/local/lib/python3.8/site-packages/uhd/imgbuilder/templates/modules/device_io_ports.v.mako > -- Installing: > /usr/local/lib/python3.8/site-packages/uhd/imgbuilder/templates/modules/chdr_xb_sep_transport.v.mako > -- Installing: > /usr/local/lib/python3.8/site-packages/uhd/imgbuilder/templates/modules/rfnoc_block.v.mako > -- Installing: > /usr/local/lib/python3.8/site-packages/uhd/imgbuilder/templates/modules/drive_unused_ports.v.mako > -- Installing: > /usr/local/lib/python3.8/site-packages/uhd/imgbuilder/templates/modules/static_router.v.mako > -- Installing: > /usr/local/lib/python3.8/site-packages/uhd/imgbuilder/templates/modules/stream_endpoints.v.mako > -- Installing: > /usr/local/lib/python3.8/site-packages/uhd/imgbuilder/templates/modules/sep_xb_wires.v.mako > -- Installing: > /usr/local/lib/python3.8/site-packages/uhd/imgbuilder/templates/modules/connect_clk_domains.v.mako > -- Installing: > /usr/local/lib/python3.8/site-packages/uhd/imgbuilder/image_builder.py > > On Wed, Mar 1, 2023 at 11:52 AM AERMAN TUERXUN. < > armantursun@g.ecc.u-tokyo.ac.jp> wrote: > >> Hi USRP users, >> >> I am currently developing an OOT RFNoC module. >> When I tried to build a custom image, it gave me errors as below. >> I checked the python path, and it seems fine. >> Is there anyone that has any idea of the reason for this? >> I am using n310 with uhd v4.2.0.0. >> (I checked with uhd4.0, and didn't encounter this problem). >> >> Thanks in advance. >> Best regards. >> >> Traceback (most recent call last): >> File "/usr/local/bin/rfnoc_image_builder", line 29, in <module> >> from uhd.imgbuilder import image_builder >> ModuleNotFoundError: No module named 'uhd' >> make[3]: *** [icores/CMakeFiles/n310_rfnoc_image_core.dir/build.make:57: >> icores/CMakeFiles/n310_rfnoc_image_core] Error 1 >> make[2]: *** [CMakeFiles/Makefile2:300: >> icores/CMakeFiles/n310_rfnoc_image_core.dir/all] Error 2 >> make[1]: *** [CMakeFiles/Makefile2:307: >> icores/CMakeFiles/n310_rfnoc_image_core.dir/rule] Error 2 >> make: *** [Makefile:203: n310_rfnoc_image_core] Error 2 >> >> >> > _______________________________________________ > USRP-users mailing list -- usrp-users@lists.ettus.com > To unsubscribe send an email to usrp-users-leave@lists.ettus.com > > Maybe your ld.so.conf doesn't include /usr/local/lib, or you didn't "sudo > ldconfig" after doing the install? > > What's in your PYTHONPATH? Is that path actually *exported* or did you > set it locally in your .bashrc (or equivalent). > > If you manually go into python and: > > import uhd > > What happens? > > > _______________________________________________ > USRP-users mailing list -- usrp-users@lists.ettus.com > To unsubscribe send an email to usrp-users-leave@lists.ettus.com >

Hi I am getting the same error when i am trying to run “rfnoc_image_builder” command. could you please tell me how to resolve this issue. as i am new researcher in this feild

On 06/12/2023 11:45, engr.muhd.hassan@gmail.com wrote: > > Hi I am getting the same error when i am trying to run > “rfnoc_image_builder” command. could you please tell me how to resolve > this issue. as i am new researcher in this feild > > We're going to need many more details.  A complete error-log from "rfnoc_image_builder" would certainly help. What OS are you using?  How did you install UHD?

sys.exit(main())

config, source, device, image_core_name, target = image_config(args)

config = yaml_utils.load_config(args.yaml_config, get_config_path())

with open(config_file) as stream:

      Installed version is Vivado v2021.1_AR76780 (64-bit)

      Installed version is Vivado v2021.1_AR76780 (64-bit)

Hi Marcus, Following is the complete terminal output grcusrp@grcusrp-ThinkPad-T470:\~$ rfnoc_image_builder -y ./e310_rfnoc_image_core.yml Traceback (most recent call last): File "/usr/local/bin/rfnoc_image_builder", line 228, in <module> sys.exit(main()) File "/usr/local/bin/rfnoc_image_builder", line 204, in main config, source, device, image_core_name, target = image_config(args) File "/usr/local/bin/rfnoc_image_builder", line 123, in image_config config = yaml_utils.load_config(args.yaml_config, get_config_path()) File "/usr/local/lib/python3.8/site-packages/uhd/imgbuilder/yaml_utils.py", line 102, in load_config with open(config_file) as stream: FileNotFoundError: \[Errno 2\] No such file or directory: './e310_rfnoc_image_core.yml' grcusrp@grcusrp-ThinkPad-T470:\~$ cd hud bash: cd: hud: No such file or directory grcusrp@grcusrp-ThinkPad-T470:\~$ cd uhd grcusrp@grcusrp-ThinkPad-T470:\~/uhd$ cd fpga grcusrp@grcusrp-ThinkPad-T470:\~/uhd/fpga$ cd usrp3 grcusrp@grcusrp-ThinkPad-T470:\~/uhd/fpga/usrp3$ cd top grcusrp@grcusrp-ThinkPad-T470:\~/uhd/fpga/usrp3/top$ cd e31x grcusrp@grcusrp-ThinkPad-T470:\~/uhd/fpga/usrp3/top/e31x$ rfnoc_image_builder -y ./e310_rfnoc_image_core.yml \[INF\] Using FPGA directory /home/grcusrp/uhd/fpga \[INF\] Selected device e310 \[INF\] Using io_signatures.yml from /usr/local/share/uhd/rfnoc/core. \[INF\] Using e310_bsp.yml from /usr/local/share/uhd/rfnoc/core. \[INF\] Adding block description from duc.yml (/usr/local/share/uhd/rfnoc/blocks). \[INF\] Adding block description from split_stream.yml (/usr/local/share/uhd/rfnoc/blocks). \[INF\] Adding block description from window.yml (/usr/local/share/uhd/rfnoc/blocks). \[INF\] Adding block description from vector_iir.yml (/usr/local/share/uhd/rfnoc/blocks). \[INF\] Adding block description from addsub.yml (/usr/local/share/uhd/rfnoc/blocks). \[INF\] Adding block description from logpwr.yml (/usr/local/share/uhd/rfnoc/blocks). \[INF\] Adding block description from null_src_sink.yml (/usr/local/share/uhd/rfnoc/blocks). \[INF\] Adding block description from fir_filter.yml (/usr/local/share/uhd/rfnoc/blocks). \[INF\] Adding block description from ddc.yml (/usr/local/share/uhd/rfnoc/blocks). \[INF\] Adding block description from moving_avg.yml (/usr/local/share/uhd/rfnoc/blocks). \[INF\] Adding block description from fft_1x64.yml (/usr/local/share/uhd/rfnoc/blocks). \[INF\] Adding block description from keep_one_in_n.yml (/usr/local/share/uhd/rfnoc/blocks). \[INF\] Adding block description from radio.yml (/usr/local/share/uhd/rfnoc/blocks). \[INF\] Adding block description from switchboard.yml (/usr/local/share/uhd/rfnoc/blocks). \[INF\] Adding block description from replay.yml (/usr/local/share/uhd/rfnoc/blocks). \[INF\] Adding block description from siggen.yml (/usr/local/share/uhd/rfnoc/blocks). \[INF\] Adding block description from axi_ram_fifo.yml (/usr/local/share/uhd/rfnoc/blocks). \[INF\] Adding block description from fosphor.yml (/usr/local/share/uhd/rfnoc/blocks). \[INF\] Plausibility checks on the current configuration \[INF\] Writing static routing table to /home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_static_router.hex \[INF\] Writing image core to /home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v \[INF\] Writing image core header to /home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.vh \[INF\] Launching build with the following settings: \[INF\] \* Build Directory: /home/grcusrp/uhd/fpga/usrp3/top/e31x \[INF\] \* Target: DRAM=1 E310_SG3 \[INF\] \* Image Core File: /home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v \[INF\] \* Edge Table File: /home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_static_router.hex Setting up a 64-bit FPGA build environment for the USRP-E31x... \- Vivado: Found (/tools/Xilinx/Vivado/2021.1/bin) Installed version is Vivado v2021.1_AR76780 (64-bit) Environment successfully initialized. make -f Makefile.e31x.inc viv_ip NAME=E310_SG3_IP ARCH=zynq PART_ID=xc7z020/clg484/-3 E310_SG3=1 TOP_MODULE=e31x EXTRA_DEFS="E310_SG3=1" DEFAULT_RFNOC_IMAGE_CORE_FILE=e310_rfnoc_image_core.v DEFAULT_EDGE_FILE=/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_static_router.hex make\[1\]: Entering directory '/home/grcusrp/uhd/fpga/usrp3/top/e31x' BUILDER: Checking tools... \* GNU bash, version 5.0.17(1)-release (x86_64-pc-linux-gnu) \* Python 3.8.10 \* Vivado v2021.1_AR76780 (64-bit) IP build for E310_SG3_IP DONE . . . make\[1\]: Leaving directory '/home/grcusrp/uhd/fpga/usrp3/top/e31x' make -f Makefile.e31x.inc bin NAME=E310_SG3 ARCH=zynq PART_ID=xc7z020/clg484/-3 E310_SG3=1 ENABLE_DRAM=1 TOP_MODULE=e31x EXTRA_DEFS=" E310_SG3=1 ENABLE_DRAM=1" DEFAULT_RFNOC_IMAGE_CORE_FILE=e310_rfnoc_image_core.v DEFAULT_EDGE_FILE=/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_static_router.hex make\[1\]: Entering directory '/home/grcusrp/uhd/fpga/usrp3/top/e31x' BUILDER: Checking tools... \* GNU bash, version 5.0.17(1)-release (x86_64-pc-linux-gnu) \* Python 3.8.10 \* Vivado v2021.1_AR76780 (64-bit) Could not read parser configuration from: /home/grcusrp/uhd/fpga/usrp3/top/e31x/dev_config.json \[00:00:00\] Executing command: vivado -mode batch -source /home/grcusrp/uhd/fpga/usrp3/top/e31x/build_e31x.tcl -log build.log -journal e31x.jou WARNING: \[filemgmt 56-12\] File '/home/grcusrp/uhd/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_replay/rfnoc_block_replay_regs.vh' cannot be added to the project because it already exists in the project, skipping this file WARNING: \[filemgmt 56-12\] File '/home/grcusrp/uhd/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_replay/axis_replay.v' cannot be added to the project because it already exists in the project, skipping this file WARNING: \[filemgmt 56-12\] File '/home/grcusrp/uhd/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_replay/noc_shell_replay.v' cannot be added to the project because it already exists in the project, skipping this file WARNING: \[filemgmt 56-12\] File '/home/grcusrp/uhd/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_replay/rfnoc_block_replay.v' cannot be added to the project because it already exists in the project, skipping this file \[00:00:16\] Current task: Initialization +++ Current Phase: Starting \[00:00:16\] Current task: Initialization +++ Current Phase: Finished \[00:00:16\] Executing Tcl: synth_design -top e31x -part xc7z020clg484-3 -verilog_define E310_SG3=1 -verilog_define ENABLE_DRAM=1 -verilog_define GIT_HASH=32'hf5fac246 -verilog_define RFNOC_EDGE_TBL_FILE=/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_static_router.hex -verilog_define RFNOC_IMAGE_CORE_HDR=/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.vh -verilog_define UHD_FPGA_DIR=/home/grcusrp/uhd/fpga/usrp3/top/../.. \[00:00:16\] Starting Synthesis Command WARNING: \[Synth 8-2507\] parameter declaration becomes local in cam_priority_encoder with formal parameter declaration list \[/home/grcusrp/uhd/fpga/usrp3/lib/control/map/cam_priority_encoder.v:46\] WARNING: \[Synth 8-2507\] parameter declaration becomes local in cam_priority_encoder with formal parameter declaration list \[/home/grcusrp/uhd/fpga/usrp3/lib/control/map/cam_priority_encoder.v:47\] WARNING: \[Synth 8-2507\] parameter declaration becomes local in axis_data_swap with formal parameter declaration list \[/home/grcusrp/uhd/fpga/usrp3/lib/axi/axis_data_swap.v:54\] WARNING: \[Synth 8-2507\] parameter declaration becomes local in axis_data_swap with formal parameter declaration list \[/home/grcusrp/uhd/fpga/usrp3/lib/axi/axis_data_swap.v:55\] WARNING: \[Synth 8-2507\] parameter declaration becomes local in dds_freq_tune_duc with formal parameter declaration list \[/home/grcusrp/uhd/fpga/usrp3/lib/rfnoc/dds_freq_tune_duc.v:128\] WARNING: \[Synth 8-2507\] parameter declaration becomes local in axis_ctrl_crossbar_2d_mesh with formal parameter declaration list \[/home/grcusrp/uhd/fpga/usrp3/lib/rfnoc/crossbar/mesh_node_mapping.vh:7\] WARNING: \[Synth 8-2507\] parameter declaration becomes local in torus_2d_dor_router_single_sw with formal parameter declaration list \[/home/grcusrp/uhd/fpga/usrp3/lib/rfnoc/crossbar/mesh_node_mapping.vh:7\] WARNING: \[Synth 8-2507\] parameter declaration becomes local in mesh_2d_dor_router_single_sw with formal parameter declaration list \[/home/grcusrp/uhd/fpga/usrp3/lib/rfnoc/crossbar/mesh_node_mapping.vh:7\] WARNING: \[Synth 8-7071\] port 'CLKFBOUT' of module 'PLLE2_ADV' is unconnected for instance 'clkgen' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/ppsloop.v:44\] WARNING: \[Synth 8-7071\] port 'CLKOUT2' of module 'PLLE2_ADV' is unconnected for instance 'clkgen' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/ppsloop.v:44\] WARNING: \[Synth 8-7071\] port 'CLKOUT3' of module 'PLLE2_ADV' is unconnected for instance 'clkgen' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/ppsloop.v:44\] WARNING: \[Synth 8-7071\] port 'CLKOUT4' of module 'PLLE2_ADV' is unconnected for instance 'clkgen' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/ppsloop.v:44\] WARNING: \[Synth 8-7071\] port 'CLKOUT5' of module 'PLLE2_ADV' is unconnected for instance 'clkgen' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/ppsloop.v:44\] WARNING: \[Synth 8-7071\] port 'DO' of module 'PLLE2_ADV' is unconnected for instance 'clkgen' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/ppsloop.v:44\] WARNING: \[Synth 8-7071\] port 'DRDY' of module 'PLLE2_ADV' is unconnected for instance 'clkgen' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/ppsloop.v:44\] WARNING: \[Synth 8-7071\] port 'CLKFBIN' of module 'PLLE2_ADV' is unconnected for instance 'clkgen' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/ppsloop.v:44\] WARNING: \[Synth 8-7071\] port 'CLKIN2' of module 'PLLE2_ADV' is unconnected for instance 'clkgen' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/ppsloop.v:44\] WARNING: \[Synth 8-7071\] port 'CLKINSEL' of module 'PLLE2_ADV' is unconnected for instance 'clkgen' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/ppsloop.v:44\] WARNING: \[Synth 8-7071\] port 'DADDR' of module 'PLLE2_ADV' is unconnected for instance 'clkgen' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/ppsloop.v:44\] WARNING: \[Synth 8-7071\] port 'DCLK' of module 'PLLE2_ADV' is unconnected for instance 'clkgen' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/ppsloop.v:44\] WARNING: \[Synth 8-7071\] port 'DEN' of module 'PLLE2_ADV' is unconnected for instance 'clkgen' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/ppsloop.v:44\] WARNING: \[Synth 8-7071\] port 'DI' of module 'PLLE2_ADV' is unconnected for instance 'clkgen' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/ppsloop.v:44\] WARNING: \[Synth 8-7071\] port 'DWE' of module 'PLLE2_ADV' is unconnected for instance 'clkgen' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/ppsloop.v:44\] WARNING: \[Synth 8-7023\] instance 'clkgen' of module 'PLLE2_ADV' has 21 connections declared, but only 6 given \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/ppsloop.v:44\] WARNING: \[Synth 8-7071\] port 'reg_wr_keep' of module 'axil_regport_master' is unconnected for instance 'eth_dma_reg_mst_i' \[/home/grcusrp/uhd/fpga/usrp3/lib/rfnoc/xport/eth_internal.v:128\] WARNING: \[Synth 8-7023\] instance 'eth_dma_reg_mst_i' of module 'axil_regport_master' has 28 connections declared, but only 27 given \[/home/grcusrp/uhd/fpga/usrp3/lib/rfnoc/xport/eth_internal.v:128\] WARNING: \[Synth 8-7071\] port 'output_unencoded' of module 'cam_priority_encoder' is unconnected for instance 'priority_encoder_inst1' \[/home/grcusrp/uhd/fpga/usrp3/lib/control/map/cam_priority_encoder.v:67\] WARNING: \[Synth 8-7023\] instance 'priority_encoder_inst1' of module 'cam_priority_encoder' has 4 connections declared, but only 3 given \[/home/grcusrp/uhd/fpga/usrp3/lib/control/map/cam_priority_encoder.v:67\] WARNING: \[Synth 8-693\] zero replication count - replication ignored \[/home/grcusrp/uhd/fpga/usrp3/lib/control/map/cam_priority_encoder.v:77\] WARNING: \[Synth 8-7071\] port 'output_unencoded' of module 'cam_priority_encoder' is unconnected for instance 'priority_encoder_inst2' \[/home/grcusrp/uhd/fpga/usrp3/lib/control/map/cam_priority_encoder.v:76\] WARNING: \[Synth 8-7023\] instance 'priority_encoder_inst2' of module 'cam_priority_encoder' has 4 connections declared, but only 3 given \[/home/grcusrp/uhd/fpga/usrp3/lib/control/map/cam_priority_encoder.v:76\] WARNING: \[Synth 8-7071\] port 'output_unencoded' of module 'cam_priority_encoder' is unconnected for instance 'priority_encoder_inst1' \[/home/grcusrp/uhd/fpga/usrp3/lib/control/map/cam_priority_encoder.v:67\] WARNING: \[Synth 8-7023\] instance 'priority_encoder_inst1' of module 'cam_priority_encoder' has 4 connections declared, but only 3 given \[/home/grcusrp/uhd/fpga/usrp3/lib/control/map/cam_priority_encoder.v:67\] WARNING: \[Synth 8-693\] zero replication count - replication ignored \[/home/grcusrp/uhd/fpga/usrp3/lib/control/map/cam_priority_encoder.v:77\] WARNING: \[Synth 8-7071\] port 'output_unencoded' of module 'cam_priority_encoder' is unconnected for instance 'priority_encoder_inst2' \[/home/grcusrp/uhd/fpga/usrp3/lib/control/map/cam_priority_encoder.v:76\] WARNING: \[Synth 8-7023\] instance 'priority_encoder_inst2' of module 'cam_priority_encoder' has 4 connections declared, but only 3 given \[/home/grcusrp/uhd/fpga/usrp3/lib/control/map/cam_priority_encoder.v:76\] WARNING: \[Synth 8-7071\] port 'output_unencoded' of module 'cam_priority_encoder' is unconnected for instance 'priority_encoder_inst1' \[/home/grcusrp/uhd/fpga/usrp3/lib/control/map/cam_priority_encoder.v:67\] WARNING: \[Synth 8-7023\] instance 'priority_encoder_inst1' of module 'cam_priority_encoder' has 4 connections declared, but only 3 given \[/home/grcusrp/uhd/fpga/usrp3/lib/control/map/cam_priority_encoder.v:67\] WARNING: \[Synth 8-693\] zero replication count - replication ignored \[/home/grcusrp/uhd/fpga/usrp3/lib/control/map/cam_priority_encoder.v:77\] WARNING: \[Synth 8-7071\] port 'output_unencoded' of module 'cam_priority_encoder' is unconnected for instance 'priority_encoder_inst2' \[/home/grcusrp/uhd/fpga/usrp3/lib/control/map/cam_priority_encoder.v:76\] WARNING: \[Synth 8-7023\] instance 'priority_encoder_inst2' of module 'cam_priority_encoder' has 4 connections declared, but only 3 given \[/home/grcusrp/uhd/fpga/usrp3/lib/control/map/cam_priority_encoder.v:76\] WARNING: \[Synth 8-7071\] port 'output_unencoded' of module 'cam_priority_encoder' is unconnected for instance 'priority_encoder_inst1' \[/home/grcusrp/uhd/fpga/usrp3/lib/control/map/cam_priority_encoder.v:67\] WARNING: \[Synth 8-7023\] instance 'priority_encoder_inst1' of module 'cam_priority_encoder' has 4 connections declared, but only 3 given \[/home/grcusrp/uhd/fpga/usrp3/lib/control/map/cam_priority_encoder.v:67\] WARNING: \[Synth 8-693\] zero replication count - replication ignored \[/home/grcusrp/uhd/fpga/usrp3/lib/control/map/cam_priority_encoder.v:77\] WARNING: \[Synth 8-7071\] port 'output_unencoded' of module 'cam_priority_encoder' is unconnected for instance 'priority_encoder_inst2' \[/home/grcusrp/uhd/fpga/usrp3/lib/control/map/cam_priority_encoder.v:76\] WARNING: \[Synth 8-7023\] instance 'priority_encoder_inst2' of module 'cam_priority_encoder' has 4 connections declared, but only 3 given \[/home/grcusrp/uhd/fpga/usrp3/lib/control/map/cam_priority_encoder.v:76\] WARNING: \[Synth 8-7071\] port 'output_unencoded' of module 'cam_priority_encoder' is unconnected for instance 'priority_encoder_inst1' \[/home/grcusrp/uhd/fpga/usrp3/lib/control/map/cam_priority_encoder.v:67\] WARNING: \[Synth 8-7023\] instance 'priority_encoder_inst1' of module 'cam_priority_encoder' has 4 connections declared, but only 3 given \[/home/grcusrp/uhd/fpga/usrp3/lib/control/map/cam_priority_encoder.v:67\] WARNING: \[Synth 8-693\] zero replication count - replication ignored \[/home/grcusrp/uhd/fpga/usrp3/lib/control/map/cam_priority_encoder.v:77\] WARNING: \[Synth 8-7071\] port 'output_unencoded' of module 'cam_priority_encoder' is unconnected for instance 'priority_encoder_inst2' \[/home/grcusrp/uhd/fpga/usrp3/lib/control/map/cam_priority_encoder.v:76\] WARNING: \[Synth 8-7023\] instance 'priority_encoder_inst2' of module 'cam_priority_encoder' has 4 connections declared, but only 3 given \[/home/grcusrp/uhd/fpga/usrp3/lib/control/map/cam_priority_encoder.v:76\] WARNING: \[Synth 8-689\] width (32) of port connection 's_axi_awaddr' does not match port width (14) of module 'eth_internal' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x.v:440\] WARNING: \[Synth 8-689\] width (32) of port connection 's_axi_araddr' does not match port width (14) of module 'eth_internal' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x.v:453\] WARNING: \[Synth 8-7071\] port 'm_axi_awprot' of module 'e31x_ps_bd_auto_cc_2' is unconnected for instance 'auto_cc' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/synth/e31x_ps_bd.v:3225\] WARNING: \[Synth 8-7071\] port 'm_axi_wstrb' of module 'e31x_ps_bd_auto_cc_2' is unconnected for instance 'auto_cc' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/synth/e31x_ps_bd.v:3225\] WARNING: \[Synth 8-7071\] port 'm_axi_arprot' of module 'e31x_ps_bd_auto_cc_2' is unconnected for instance 'auto_cc' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/synth/e31x_ps_bd.v:3225\] WARNING: \[Synth 8-7023\] instance 'auto_cc' of module 'e31x_ps_bd_auto_cc_2' has 42 connections declared, but only 39 given \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/synth/e31x_ps_bd.v:3225\] WARNING: \[Synth 8-7071\] port 'aclk2x' of module 'axi_register_slice_v2_1_24_axi_register_slice' is unconnected for instance 'SI_REG' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/ipshared/6e0d/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4392\] WARNING: \[Synth 8-7023\] instance 'SI_REG' of module 'axi_register_slice_v2_1_24_axi_register_slice' has 93 connections declared, but only 92 given \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/ipshared/6e0d/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4392\] WARNING: \[Synth 8-7071\] port 'aclk2x' of module 'axi_register_slice_v2_1_24_axi_register_slice' is unconnected for instance 'MI_REG' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/ipshared/6e0d/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4647\] WARNING: \[Synth 8-7023\] instance 'MI_REG' of module 'axi_register_slice_v2_1_24_axi_register_slice' has 93 connections declared, but only 92 given \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/ipshared/6e0d/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4647\] WARNING: \[Synth 8-7071\] port 'axi_dma_tstvec' of module 'e31x_ps_bd_axi_dma_eth_internal_0' is unconnected for instance 'axi_dma_eth_internal' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/synth/e31x_ps_bd.v:420\] WARNING: \[Synth 8-7023\] instance 'axi_dma_eth_internal' of module 'e31x_ps_bd_axi_dma_eth_internal_0' has 94 connections declared, but only 93 given \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/synth/e31x_ps_bd.v:420\] WARNING: \[Synth 8-7071\] port 'M_AXI_GP0_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/synth/e31x_ps_bd_processing_system7_0_0.v:828\] WARNING: \[Synth 8-7071\] port 'M_AXI_GP1_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/synth/e31x_ps_bd_processing_system7_0_0.v:828\] WARNING: \[Synth 8-7071\] port 'S_AXI_GP0_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/synth/e31x_ps_bd_processing_system7_0_0.v:828\] WARNING: \[Synth 8-7071\] port 'S_AXI_GP1_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/synth/e31x_ps_bd_processing_system7_0_0.v:828\] WARNING: \[Synth 8-7071\] port 'S_AXI_ACP_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/synth/e31x_ps_bd_processing_system7_0_0.v:828\] WARNING: \[Synth 8-7071\] port 'S_AXI_HP0_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/synth/e31x_ps_bd_processing_system7_0_0.v:828\] WARNING: \[Synth 8-7071\] port 'S_AXI_HP1_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/synth/e31x_ps_bd_processing_system7_0_0.v:828\] WARNING: \[Synth 8-7071\] port 'S_AXI_HP2_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/synth/e31x_ps_bd_processing_system7_0_0.v:828\] WARNING: \[Synth 8-7071\] port 'S_AXI_HP3_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/synth/e31x_ps_bd_processing_system7_0_0.v:828\] WARNING: \[Synth 8-7071\] port 'DMA0_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/synth/e31x_ps_bd_processing_system7_0_0.v:828\] WARNING: \[Synth 8-7071\] port 'DMA1_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/synth/e31x_ps_bd_processing_system7_0_0.v:828\] WARNING: \[Synth 8-7071\] port 'DMA2_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/synth/e31x_ps_bd_processing_system7_0_0.v:828\] WARNING: \[Synth 8-7071\] port 'DMA3_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/synth/e31x_ps_bd_processing_system7_0_0.v:828\] WARNING: \[Synth 8-7023\] instance 'inst' of module 'processing_system7_v5_5_processing_system7' has 685 connections declared, but only 672 given \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/synth/e31x_ps_bd_processing_system7_0_0.v:828\] WARNING: \[Synth 8-7071\] port 'S_AXI_GP0_BID' of module 'e31x_ps_bd_processing_system7_0_0' is unconnected for instance 'processing_system7_0' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/synth/e31x_ps_bd.v:1478\] WARNING: \[Synth 8-7071\] port 'S_AXI_GP0_RID' of module 'e31x_ps_bd_processing_system7_0_0' is unconnected for instance 'processing_system7_0' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/synth/e31x_ps_bd.v:1478\] WARNING: \[Synth 8-7071\] port 'S_AXI_HP1_ARREADY' of module 'e31x_ps_bd_processing_system7_0_0' is unconnected for instance 'processing_system7_0' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/synth/e31x_ps_bd.v:1478\] WARNING: \[Synth 8-7071\] port 'S_AXI_HP1_RLAST' of module 'e31x_ps_bd_processing_system7_0_0' is unconnected for instance 'processing_system7_0' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/synth/e31x_ps_bd.v:1478\] WARNING: \[Synth 8-7071\] port 'S_AXI_HP1_RVALID' of module 'e31x_ps_bd_processing_system7_0_0' is unconnected for instance 'processing_system7_0' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/synth/e31x_ps_bd.v:1478\] WARNING: \[Synth 8-7071\] port 'S_AXI_HP1_RRESP' of module 'e31x_ps_bd_processing_system7_0_0' is unconnected for instance 'processing_system7_0' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/synth/e31x_ps_bd.v:1478\] WARNING: \[Synth 8-7071\] port 'S_AXI_HP1_BID' of module 'e31x_ps_bd_processing_system7_0_0' is unconnected for instance 'processing_system7_0' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/synth/e31x_ps_bd.v:1478\] WARNING: \[Synth 8-7071\] port 'S_AXI_HP1_RID' of module 'e31x_ps_bd_processing_system7_0_0' is unconnected for instance 'processing_system7_0' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/synth/e31x_ps_bd.v:1478\] WARNING: \[Synth 8-7071\] port 'S_AXI_HP1_RDATA' of module 'e31x_ps_bd_processing_system7_0_0' is unconnected for instance 'processing_system7_0' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/synth/e31x_ps_bd.v:1478\] WARNING: \[Synth 8-7071\] port 'S_AXI_HP1_RCOUNT' of module 'e31x_ps_bd_processing_system7_0_0' is unconnected for instance 'processing_system7_0' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/synth/e31x_ps_bd.v:1478\] WARNING: \[Synth 8-7071\] port 'S_AXI_HP1_WCOUNT' of module 'e31x_ps_bd_processing_system7_0_0' is unconnected for instance 'processing_system7_0' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/synth/e31x_ps_bd.v:1478\] WARNING: \[Synth 8-7071\] port 'S_AXI_HP1_RACOUNT' of module 'e31x_ps_bd_processing_system7_0_0' is unconnected for instance 'processing_system7_0' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/synth/e31x_ps_bd.v:1478\] WARNING: \[Synth 8-7071\] port 'S_AXI_HP1_WACOUNT' of module 'e31x_ps_bd_processing_system7_0_0' is unconnected for instance 'processing_system7_0' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/synth/e31x_ps_bd.v:1478\] WARNING: \[Synth 8-7071\] port 'S_AXI_HP2_AWREADY' of module 'e31x_ps_bd_processing_system7_0_0' is unconnected for instance 'processing_system7_0' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/synth/e31x_ps_bd.v:1478\] WARNING: \[Synth 8-7071\] port 'S_AXI_HP2_BVALID' of module 'e31x_ps_bd_processing_system7_0_0' is unconnected for instance 'processing_system7_0' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/synth/e31x_ps_bd.v:1478\] WARNING: \[Synth 8-7071\] port 'S_AXI_HP2_WREADY' of module 'e31x_ps_bd_processing_system7_0_0' is unconnected for instance 'processing_system7_0' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/synth/e31x_ps_bd.v:1478\] WARNING: \[Synth 8-7071\] port 'S_AXI_HP2_BRESP' of module 'e31x_ps_bd_processing_system7_0_0' is unconnected for instance 'processing_system7_0' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/synth/e31x_ps_bd.v:1478\] WARNING: \[Synth 8-7071\] port 'S_AXI_HP2_BID' of module 'e31x_ps_bd_processing_system7_0_0' is unconnected for instance 'processing_system7_0' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/synth/e31x_ps_bd.v:1478\] WARNING: \[Synth 8-7071\] port 'S_AXI_HP2_RID' of module 'e31x_ps_bd_processing_system7_0_0' is unconnected for instance 'processing_system7_0' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/synth/e31x_ps_bd.v:1478\] WARNING: \[Synth 8-7071\] port 'S_AXI_HP2_RCOUNT' of module 'e31x_ps_bd_processing_system7_0_0' is unconnected for instance 'processing_system7_0' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/synth/e31x_ps_bd.v:1478\] WARNING: \[Synth 8-7071\] port 'S_AXI_HP2_WCOUNT' of module 'e31x_ps_bd_processing_system7_0_0' is unconnected for instance 'processing_system7_0' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/synth/e31x_ps_bd.v:1478\] WARNING: \[Synth 8-7071\] port 'S_AXI_HP2_RACOUNT' of module 'e31x_ps_bd_processing_system7_0_0' is unconnected for instance 'processing_system7_0' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/synth/e31x_ps_bd.v:1478\] WARNING: \[Synth 8-7071\] port 'S_AXI_HP2_WACOUNT' of module 'e31x_ps_bd_processing_system7_0_0' is unconnected for instance 'processing_system7_0' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/synth/e31x_ps_bd.v:1478\] WARNING: \[Synth 8-7023\] instance 'processing_system7_0' of module 'e31x_ps_bd_processing_system7_0_0' has 229 connections declared, but only 206 given \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/synth/e31x_ps_bd.v:1478\] WARNING: \[Synth 8-7071\] port 'mb_reset' of module 'bd_cc08_psr_aclk_0' is unconnected for instance 'psr_aclk' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_smartconnect_dma_0/bd_0/synth/bd_cc08.v:798\] WARNING: \[Synth 8-7071\] port 'bus_struct_reset' of module 'bd_cc08_psr_aclk_0' is unconnected for instance 'psr_aclk' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_smartconnect_dma_0/bd_0/synth/bd_cc08.v:798\] WARNING: \[Synth 8-7071\] port 'peripheral_reset' of module 'bd_cc08_psr_aclk_0' is unconnected for instance 'psr_aclk' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_smartconnect_dma_0/bd_0/synth/bd_cc08.v:798\] WARNING: \[Synth 8-7071\] port 'peripheral_aresetn' of module 'bd_cc08_psr_aclk_0' is unconnected for instance 'psr_aclk' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_smartconnect_dma_0/bd_0/synth/bd_cc08.v:798\] WARNING: \[Synth 8-7023\] instance 'psr_aclk' of module 'bd_cc08_psr_aclk_0' has 10 connections declared, but only 6 given \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_smartconnect_dma_0/bd_0/synth/bd_cc08.v:798\] WARNING: \[Synth 8-7071\] port 'm_axi_awburst' of module 'bd_cc08_s00tr_0' is unconnected for instance 's00_transaction_regulator' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_smartconnect_dma_0/bd_0/synth/bd_cc08.v:1706\] WARNING: \[Synth 8-7071\] port 'm_axi_arburst' of module 'bd_cc08_s00tr_0' is unconnected for instance 's00_transaction_regulator' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_smartconnect_dma_0/bd_0/synth/bd_cc08.v:1706\] WARNING: \[Synth 8-7023\] instance 's00_transaction_regulator' of module 'bd_cc08_s00tr_0' has 82 connections declared, but only 80 given \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_smartconnect_dma_0/bd_0/synth/bd_cc08.v:1706\] WARNING: \[Synth 8-6104\] Input port 'PS_CLK' has an internal driver \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x.v:541\] WARNING: \[Synth 8-6104\] Input port 'PS_PORB' has an internal driver \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x.v:542\] WARNING: \[Synth 8-6104\] Input port 'PS_SRSTB' has an internal driver \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x.v:543\] WARNING: \[Synth 8-689\] width (32) of port connection 'm_axi_eth_internal_araddr' does not match port width (31) of module 'e31x_ps_bd' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x.v:577\] WARNING: \[Synth 8-689\] width (32) of port connection 'm_axi_eth_internal_awaddr' does not match port width (31) of module 'e31x_ps_bd' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x.v:581\] WARNING: \[Synth 8-689\] width (1) of port connection 'm_axi_xbar_arprot' does not match port width (3) of module 'e31x_ps_bd' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x.v:611\] WARNING: \[Synth 8-689\] width (1) of port connection 'm_axi_xbar_awprot' does not match port width (3) of module 'e31x_ps_bd' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x.v:615\] WARNING: \[Synth 8-7071\] port 'CE' of module 'BUFR' is unconnected for instance 'bufr_rx_clk' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_io.v:44\] WARNING: \[Synth 8-7071\] port 'CLR' of module 'BUFR' is unconnected for instance 'bufr_rx_clk' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_io.v:44\] WARNING: \[Synth 8-7023\] instance 'bufr_rx_clk' of module 'BUFR' has 4 connections declared, but only 2 given \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_io.v:44\] WARNING: \[Synth 8-7071\] port 'deepsleep' of module 'blk_mem_gen_v8_4_4' is unconnected for instance 'w_buffer' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/ipshared/3d13/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:10152\] WARNING: \[Synth 8-7071\] port 'shutdown' of module 'blk_mem_gen_v8_4_4' is unconnected for instance 'w_buffer' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/ipshared/3d13/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:10152\] WARNING: \[Synth 8-7071\] port 'rsta_busy' of module 'blk_mem_gen_v8_4_4' is unconnected for instance 'w_buffer' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/ipshared/3d13/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:10152\] WARNING: \[Synth 8-7071\] port 'rstb_busy' of module 'blk_mem_gen_v8_4_4' is unconnected for instance 'w_buffer' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/ipshared/3d13/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:10152\] WARNING: \[Synth 8-7023\] instance 'w_buffer' of module 'blk_mem_gen_v8_4_4' has 63 connections declared, but only 59 given \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/ipshared/3d13/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:10152\] WARNING: \[Synth 8-7071\] port 'aclk2x' of module 'axi_register_slice_v2_1_24_axi_register_slice' is unconnected for instance 's_aw_reg' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/ipshared/3d13/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:10660\] WARNING: \[Synth 8-7023\] instance 's_aw_reg' of module 'axi_register_slice_v2_1_24_axi_register_slice' has 93 connections declared, but only 92 given \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/ipshared/3d13/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:10660\] WARNING: \[Synth 8-7071\] port 'aclk2x' of module 'axi_register_slice_v2_1_24_axi_register_slice' is unconnected for instance 'si_register_slice_inst' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/ipshared/3d13/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:7379\] WARNING: \[Synth 8-7023\] instance 'si_register_slice_inst' of module 'axi_register_slice_v2_1_24_axi_register_slice' has 93 connections declared, but only 92 given \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/ipshared/3d13/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:7379\] WARNING: \[Synth 8-7071\] port 'm_axi_awregion' of module 'axi_inter_2x64_128_bd_s00_width_conv_0' is unconnected for instance 's00_width_conv' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/synth/axi_inter_2x64_128_bd.v:574\] WARNING: \[Synth 8-7071\] port 'm_axi_arregion' of module 'axi_inter_2x64_128_bd_s00_width_conv_0' is unconnected for instance 's00_width_conv' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/synth/axi_inter_2x64_128_bd.v:574\] WARNING: \[Synth 8-7023\] instance 's00_width_conv' of module 'axi_inter_2x64_128_bd_s00_width_conv_0' has 78 connections declared, but only 76 given \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/synth/axi_inter_2x64_128_bd.v:574\] WARNING: \[Synth 8-7071\] port 'm_axi_awregion' of module 'axi_inter_2x64_128_bd_s01_width_conv_0' is unconnected for instance 's01_width_conv' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/synth/axi_inter_2x64_128_bd.v:651\] WARNING: \[Synth 8-7071\] port 'm_axi_arregion' of module 'axi_inter_2x64_128_bd_s01_width_conv_0' is unconnected for instance 's01_width_conv' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/synth/axi_inter_2x64_128_bd.v:651\] WARNING: \[Synth 8-7023\] instance 's01_width_conv' of module 'axi_inter_2x64_128_bd_s01_width_conv_0' has 78 connections declared, but only 76 given \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/synth/axi_inter_2x64_128_bd.v:651\] WARNING: \[Synth 8-7071\] port 'aclk2x' of module 'axi_register_slice_v2_1_24_axi_register_slice' is unconnected for instance 'reg_slice_mi' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/ipshared/3917/hdl/axi_crossbar_v2_1_vl_rfs.v:3122\] WARNING: \[Synth 8-7023\] instance 'reg_slice_mi' of module 'axi_register_slice_v2_1_24_axi_register_slice' has 93 connections declared, but only 92 given \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/ipshared/3917/hdl/axi_crossbar_v2_1_vl_rfs.v:3122\] WARNING: \[Synth 8-7071\] port 'aclk2x' of module 'axi_register_slice_v2_1_24_axi_register_slice' is unconnected for instance 'reg_slice_mi' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/ipshared/3917/hdl/axi_crossbar_v2_1_vl_rfs.v:3122\] WARNING: \[Synth 8-7023\] instance 'reg_slice_mi' of module 'axi_register_slice_v2_1_24_axi_register_slice' has 93 connections declared, but only 92 given \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/ipshared/3917/hdl/axi_crossbar_v2_1_vl_rfs.v:3122\] WARNING: \[Synth 8-7071\] port 's_axi_bid' of module 'axi_inter_2x64_128_bd_xbar_0' is unconnected for instance 'xbar' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/synth/axi_inter_2x64_128_bd.v:728\] WARNING: \[Synth 8-7071\] port 's_axi_rid' of module 'axi_inter_2x64_128_bd_xbar_0' is unconnected for instance 'xbar' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/synth/axi_inter_2x64_128_bd.v:728\] WARNING: \[Synth 8-7023\] instance 'xbar' of module 'axi_inter_2x64_128_bd_xbar_0' has 78 connections declared, but only 76 given \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/synth/axi_inter_2x64_128_bd.v:728\] WARNING: \[Synth 8-689\] width (12) of port connection 'M00_AXI_arid' does not match port width (1) of module 'axi_inter_2x64_128_bd' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_dram.v:218\] WARNING: \[Synth 8-689\] width (12) of port connection 'M00_AXI_awid' does not match port width (1) of module 'axi_inter_2x64_128_bd' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_dram.v:230\] WARNING: \[Synth 8-689\] width (12) of port connection 'M00_AXI_bid' does not match port width (1) of module 'axi_inter_2x64_128_bd' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_dram.v:239\] WARNING: \[Synth 8-689\] width (12) of port connection 'M00_AXI_rid' does not match port width (1) of module 'axi_inter_2x64_128_bd' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_dram.v:244\] WARNING: \[Synth 8-689\] width (64) of port connection 'dram_axi_araddr' does not match port width (58) of module 'e31x_dram' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:766\] WARNING: \[Synth 8-689\] width (64) of port connection 'dram_axi_awaddr' does not match port width (58) of module 'e31x_dram' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:778\] WARNING: \[Synth 8-7071\] port 'time_increment' of module 'timekeeper' is unconnected for instance 'timekeeper_i' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:664\] WARNING: \[Synth 8-7023\] instance 'timekeeper_i' of module 'timekeeper' has 15 connections declared, but only 14 given \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:664\] WARNING: \[Synth 8-693\] zero replication count - replication ignored \[/home/grcusrp/uhd/fpga/usrp3/lib/rfnoc/core/chdr_data_swapper.v:189\] WARNING: \[Synth 8-693\] zero replication count - replication ignored \[/home/grcusrp/uhd/fpga/usrp3/lib/rfnoc/core/chdr_data_swapper.v:189\] WARNING: \[Synth 8-689\] width (256) of port connection 'radio_rx_data' does not match port width (64) of module 'rfnoc_block_radio' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:620\] WARNING: \[Synth 8-689\] width (8) of port connection 'radio_rx_stb' does not match port width (2) of module 'rfnoc_block_radio' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:621\] WARNING: \[Synth 8-689\] width (8) of port connection 'radio_rx_running' does not match port width (2) of module 'rfnoc_block_radio' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:622\] WARNING: \[Synth 8-689\] width (256) of port connection 'radio_tx_data' does not match port width (64) of module 'rfnoc_block_radio' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:623\] WARNING: \[Synth 8-689\] width (8) of port connection 'radio_tx_stb' does not match port width (2) of module 'rfnoc_block_radio' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:624\] WARNING: \[Synth 8-689\] width (8) of port connection 'radio_tx_running' does not match port width (2) of module 'rfnoc_block_radio' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:625\] WARNING: \[Synth 8-689\] width (4) of port connection 'm_axi_awid' does not match port width (2) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:719\] WARNING: \[Synth 8-689\] width (192) of port connection 'm_axi_awaddr' does not match port width (60) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:720\] WARNING: \[Synth 8-689\] width (32) of port connection 'm_axi_awlen' does not match port width (16) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:721\] WARNING: \[Synth 8-689\] width (12) of port connection 'm_axi_awsize' does not match port width (6) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:722\] WARNING: \[Synth 8-689\] width (8) of port connection 'm_axi_awburst' does not match port width (4) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:723\] WARNING: \[Synth 8-689\] width (4) of port connection 'm_axi_awlock' does not match port width (2) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:724\] WARNING: \[Synth 8-689\] width (16) of port connection 'm_axi_awcache' does not match port width (8) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:725\] WARNING: \[Synth 8-689\] width (12) of port connection 'm_axi_awprot' does not match port width (6) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:726\] WARNING: \[Synth 8-689\] width (16) of port connection 'm_axi_awqos' does not match port width (8) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:727\] WARNING: \[Synth 8-689\] width (16) of port connection 'm_axi_awregion' does not match port width (8) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:728\] WARNING: \[Synth 8-689\] width (4) of port connection 'm_axi_awuser' does not match port width (2) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:729\] WARNING: \[Synth 8-689\] width (4) of port connection 'm_axi_awvalid' does not match port width (2) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:730\] WARNING: \[Synth 8-689\] width (4) of port connection 'm_axi_awready' does not match port width (2) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:731\] WARNING: \[Synth 8-689\] width (2048) of port connection 'm_axi_wdata' does not match port width (128) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:732\] WARNING: \[Synth 8-689\] width (256) of port connection 'm_axi_wstrb' does not match port width (16) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:733\] WARNING: \[Synth 8-689\] width (4) of port connection 'm_axi_wlast' does not match port width (2) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:734\] WARNING: \[Synth 8-689\] width (4) of port connection 'm_axi_wuser' does not match port width (2) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:735\] WARNING: \[Synth 8-689\] width (4) of port connection 'm_axi_wvalid' does not match port width (2) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:736\] WARNING: \[Synth 8-689\] width (4) of port connection 'm_axi_wready' does not match port width (2) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:737\] WARNING: \[Synth 8-689\] width (4) of port connection 'm_axi_bid' does not match port width (2) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:738\] WARNING: \[Synth 8-689\] width (8) of port connection 'm_axi_bresp' does not match port width (4) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:739\] WARNING: \[Synth 8-689\] width (4) of port connection 'm_axi_buser' does not match port width (2) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:740\] WARNING: \[Synth 8-689\] width (4) of port connection 'm_axi_bvalid' does not match port width (2) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:741\] WARNING: \[Synth 8-689\] width (4) of port connection 'm_axi_bready' does not match port width (2) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:742\] WARNING: \[Synth 8-689\] width (4) of port connection 'm_axi_arid' does not match port width (2) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:743\] WARNING: \[Synth 8-689\] width (192) of port connection 'm_axi_araddr' does not match port width (60) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:744\] WARNING: \[Synth 8-689\] width (32) of port connection 'm_axi_arlen' does not match port width (16) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:745\] WARNING: \[Synth 8-689\] width (12) of port connection 'm_axi_arsize' does not match port width (6) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:746\] WARNING: \[Synth 8-689\] width (8) of port connection 'm_axi_arburst' does not match port width (4) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:747\] WARNING: \[Synth 8-689\] width (4) of port connection 'm_axi_arlock' does not match port width (2) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:748\] WARNING: \[Synth 8-689\] width (16) of port connection 'm_axi_arcache' does not match port width (8) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:749\] WARNING: \[Synth 8-689\] width (12) of port connection 'm_axi_arprot' does not match port width (6) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:750\] WARNING: \[Synth 8-689\] width (16) of port connection 'm_axi_arqos' does not match port width (8) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:751\] WARNING: \[Synth 8-689\] width (16) of port connection 'm_axi_arregion' does not match port width (8) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:752\] WARNING: \[Synth 8-689\] width (4) of port connection 'm_axi_aruser' does not match port width (2) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:753\] WARNING: \[Synth 8-689\] width (4) of port connection 'm_axi_arvalid' does not match port width (2) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:754\] WARNING: \[Synth 8-689\] width (4) of port connection 'm_axi_arready' does not match port width (2) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:755\] WARNING: \[Synth 8-689\] width (4) of port connection 'm_axi_rid' does not match port width (2) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:756\] WARNING: \[Synth 8-689\] width (2048) of port connection 'm_axi_rdata' does not match port width (128) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:757\] WARNING: \[Synth 8-689\] width (8) of port connection 'm_axi_rresp' does not match port width (4) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:758\] WARNING: \[Synth 8-689\] width (4) of port connection 'm_axi_rlast' does not match port width (2) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:759\] WARNING: \[Synth 8-689\] width (4) of port connection 'm_axi_ruser' does not match port width (2) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:760\] WARNING: \[Synth 8-689\] width (4) of port connection 'm_axi_rvalid' does not match port width (2) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:761\] WARNING: \[Synth 8-689\] width (4) of port connection 'm_axi_rready' does not match port width (2) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:762\] WARNING: \[Synth 8-689\] width (2) of port connection 'radio_rx_running' does not match port width (8) of module 'rfnoc_image_core' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:839\] WARNING: \[Synth 8-689\] width (64) of port connection 'radio_tx_data' does not match port width (256) of module 'rfnoc_image_core' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:841\] WARNING: \[Synth 8-689\] width (2) of port connection 'radio_tx_running' does not match port width (8) of module 'rfnoc_image_core' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:842\] WARNING: \[Synth 8-689\] width (2) of port connection 'm_axi_awid' does not match port width (4) of module 'rfnoc_image_core' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:844\] WARNING: \[Synth 8-689\] width (64) of port connection 'm_axi_awaddr' does not match port width (192) of module 'rfnoc_image_core' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:845\] WARNING: \[Synth 8-689\] width (16) of port connection 'm_axi_awlen' does not match port width (32) of module 'rfnoc_image_core' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:846\] WARNING: \[Synth 8-689\] width (6) of port connection 'm_axi_awsize' does not match port width (12) of module 'rfnoc_image_core' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:847\] WARNING: \[Synth 8-689\] width (4) of port connection 'm_axi_awburst' does not match port width (8) of module 'rfnoc_image_core' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:848\] WARNING: \[Synth 8-689\] width (2) of port connection 'm_axi_awlock' does not match port width (4) of module 'rfnoc_image_core' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:849\] WARNING: \[Synth 8-689\] width (8) of port connection 'm_axi_awcache' does not match port width (16) of module 'rfnoc_image_core' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:850\] WARNING: \[Synth 8-689\] width (6) of port connection 'm_axi_awprot' does not match port width (12) of module 'rfnoc_image_core' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:851\] WARNING: \[Synth 8-689\] width (8) of port connection 'm_axi_awqos' does not match port width (16) of module 'rfnoc_image_core' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:852\] WARNING: \[Synth 8-689\] width (8) of port connection 'm_axi_awregion' does not match port width (16) of module 'rfnoc_image_core' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:853\] WARNING: \[Synth 8-689\] width (2) of port connection 'm_axi_awvalid' does not match port width (4) of module 'rfnoc_image_core' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:855\] WARNING: \[Synth 8-689\] width (128) of port connection 'm_axi_wdata' does not match port width (2048) of module 'rfnoc_image_core' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:857\] WARNING: \[Synth 8-689\] width (16) of port connection 'm_axi_wstrb' does not match port width (256) of module 'rfnoc_image_core' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:858\] WARNING: \[Synth 8-689\] width (2) of port connection 'm_axi_wlast' does not match port width (4) of module 'rfnoc_image_core' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:859\] WARNING: \[Synth 8-689\] width (2) of port connection 'm_axi_wvalid' does not match port width (4) of module 'rfnoc_image_core' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:861\] WARNING: \[Synth 8-689\] width (2) of port connection 'm_axi_bready' does not match port width (4) of module 'rfnoc_image_core' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:867\] WARNING: \[Synth 8-689\] width (2) of port connection 'm_axi_arid' does not match port width (4) of module 'rfnoc_image_core' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:868\] WARNING: \[Synth 8-689\] width (64) of port connection 'm_axi_araddr' does not match port width (192) of module 'rfnoc_image_core' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:869\] WARNING: \[Synth 8-689\] width (16) of port connection 'm_axi_arlen' does not match port width (32) of module 'rfnoc_image_core' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:870\] WARNING: \[Synth 8-689\] width (6) of port connection 'm_axi_arsize' does not match port width (12) of module 'rfnoc_image_core' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:871\] WARNING: \[Synth 8-689\] width (4) of port connection 'm_axi_arburst' does not match port width (8) of module 'rfnoc_image_core' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:872\] WARNING: \[Synth 8-689\] width (2) of port connection 'm_axi_arlock' does not match port width (4) of module 'rfnoc_image_core' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:873\] WARNING: \[Synth 8-689\] width (8) of port connection 'm_axi_arcache' does not match port width (16) of module 'rfnoc_image_core' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:874\] WARNING: \[Synth 8-689\] width (6) of port connection 'm_axi_arprot' does not match port width (12) of module 'rfnoc_image_core' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:875\] WARNING: \[Synth 8-689\] width (8) of port connection 'm_axi_arqos' does not match port width (16) of module 'rfnoc_image_core' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:876\] WARNING: \[Synth 8-689\] width (8) of port connection 'm_axi_arregion' does not match port width (16) of module 'rfnoc_image_core' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:877\] WARNING: \[Synth 8-689\] width (2) of port connection 'm_axi_arvalid' does not match port width (4) of module 'rfnoc_image_core' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:879\] WARNING: \[Synth 8-689\] width (2) of port connection 'm_axi_rready' does not match port width (4) of module 'rfnoc_image_core' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:887\] WARNING: \[Synth 8-689\] width (32) of port connection 's_axi_awaddr' does not match port width (14) of module 'e31x_core' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x.v:893\] WARNING: \[Synth 8-689\] width (32) of port connection 's_axi_araddr' does not match port width (14) of module 'e31x_core' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x.v:906\] WARNING: \[Synth 8-689\] width (6) of port connection 'occupied' does not match port width (16) of module 'axi_fifo_bram__parameterized10' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/axi_pmu.v:167\] WARNING: \[Synth 8-689\] width (6) of port connection 'space' does not match port width (16) of module 'axi_fifo_bram__parameterized10' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/axi_pmu.v:168\] \[00:01:17\] Current task: Synthesis +++ Current Phase: Starting CRITICAL WARNING: \[Netlist 29-160\] Cannot set property 'iostandard', because the property does not exist for objects of type 'pin'. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/e31x_ps_bd_processing_system7_0_0.xdc:405\] CRITICAL WARNING: \[Netlist 29-160\] Cannot set property 'PACKAGE_PIN', because the property does not exist for objects of type 'pin'. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/e31x_ps_bd_processing_system7_0_0.xdc:406\] CRITICAL WARNING: \[Netlist 29-160\] Cannot set property 'slew', because the property does not exist for objects of type 'pin'. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/e31x_ps_bd_processing_system7_0_0.xdc:407\] CRITICAL WARNING: \[Netlist 29-160\] Cannot set property 'PIO_DIRECTION', because the property does not exist for objects of type 'pin'. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/e31x_ps_bd_processing_system7_0_0.xdc:408\] CRITICAL WARNING: \[Netlist 29-160\] Cannot set property 'iostandard', because the property does not exist for objects of type 'pin'. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/e31x_ps_bd_processing_system7_0_0.xdc:417\] CRITICAL WARNING: \[Netlist 29-160\] Cannot set property 'PACKAGE_PIN', because the property does not exist for objects of type 'pin'. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/e31x_ps_bd_processing_system7_0_0.xdc:418\] CRITICAL WARNING: \[Netlist 29-160\] Cannot set property 'slew', because the property does not exist for objects of type 'pin'. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/e31x_ps_bd_processing_system7_0_0.xdc:419\] CRITICAL WARNING: \[Netlist 29-160\] Cannot set property 'PIO_DIRECTION', because the property does not exist for objects of type 'pin'. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/e31x_ps_bd_processing_system7_0_0.xdc:420\] WARNING: \[Vivado 12-4702\] slew is not a supported property on input port(s). Setting is ignored. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/e31x_ps_bd_processing_system7_0_0.xdc:691\] WARNING: \[Vivado 12-4702\] slew is not a supported property on input port(s). Setting is ignored. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/e31x_ps_bd_processing_system7_0_0.xdc:694\] WARNING: \[Vivado 12-4702\] slew is not a supported property on input port(s). Setting is ignored. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/e31x_ps_bd_processing_system7_0_0.xdc:697\] CRITICAL WARNING: \[Constraints 18-1056\] Clock 'bus_clk' completely overrides clock 'clk_fpga_0'. CRITICAL WARNING: \[Constraints 18-1056\] Clock 'clk40' completely overrides clock 'clk_fpga_1'. WARNING: \[Vivado 12-508\] No pins matched 'get_pins -hierarchical -filter {NAME =\~ \*/synchronizer_false_path/stages\[0\].value_reg\[0\]\[\*\]/S}'. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_timing.xdc:141\] WARNING: \[Project 1-498\] One or more constraints failed evaluation while reading constraint file \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_timing.xdc\] and the design contains unresolved black boxes. These constraints will be read post-synthesis (as long as their source constraint file is marked as used_in_implementation) and should be applied correctly then. You should review the constraints listed in the file \[.Xil/e31x_propImpl.xdc\] and check the run log file to verify that these constraints were correctly applied. WARNING: \[XPM_CDC_GRAY: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_GRAY: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_GRAY: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_GRAY: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_GRAY: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_GRAY: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_GRAY: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_GRAY: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_GRAY: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_GRAY: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[Vivado 12-180\] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3\] WARNING: \[Vivado 12-180\] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3\] WARNING: \[Vivado 12-180\] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3\] WARNING: \[Vivado 12-180\] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3\] WARNING: \[Vivado 12-180\] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3\] WARNING: \[Timing 38-316\] Clock period '10.000' specified during out-of-context synthesis of instance 'e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/ctrlport_endpoint_i/gen_async_fifos.in_fifo_i/fifo_section\[0\].impl_srl_i' at clock pin 'rd_clk' is different from the actual clock period '5.000', this can lead to different synthesis results. WARNING: \[Timing 38-316\] Clock period '10.000' specified during out-of-context synthesis of instance 'e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/ctrlport_endpoint_i/gen_async_fifos.out_fifo_i/fifo_section\[0\].impl_srl_i' at clock pin 'wr_clk' is different from the actual clock period '5.000', this can lead to different synthesis results. WARNING: \[Timing 38-316\] Clock period '10.000' specified during out-of-context synthesis of instance 'e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_input_in\[0\].chdr_to_axis_data_in_in/flush_2clk_ctrl_i/fifo_section\[0\].impl_srl_i' at clock pin 'rd_clk' is different from the actual clock period '5.000', this can lead to different synthesis results. WARNING: \[Timing 38-316\] Clock period '10.000' specified during out-of-context synthesis of instance 'e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_input_in\[0\].chdr_to_axis_data_in_in/gen_async_info_fifo.info_fifo_i/fifo_section\[0\].impl_srl_i' at clock pin 'rd_clk' is different from the actual clock period '5.000', this can lead to different synthesis results. WARNING: \[Timing 38-316\] Clock period '10.000' specified during out-of-context synthesis of instance 'e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_input_in\[0\].chdr_to_axis_data_in_in/gen_async_info_fifo.info_fifo_i/fifo_section\[1\].impl_srl_i' at clock pin 'rd_clk' is different from the actual clock period '5.000', this can lead to different synthesis results. WARNING: \[Timing 38-316\] Clock period '10.000' specified during out-of-context synthesis of instance 'e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_input_in\[0\].chdr_to_axis_data_in_in/no_gen_axis_width_conv.gen_async_pyld_fifo.pyld_fifo_i/fifo_section\[0\].impl_srl_i' at clock pin 'rd_clk' is different from the actual clock period '5.000', this can lead to different synthesis results. WARNING: \[Timing 38-316\] Clock period '10.000' specified during out-of-context synthesis of instance 'e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_input_in\[1\].chdr_to_axis_data_in_in/flush_2clk_ctrl_i/fifo_section\[0\].impl_srl_i' at clock pin 'rd_clk' is different from the actual clock period '5.000', this can lead to different synthesis results. WARNING: \[Timing 38-316\] Clock period '10.000' specified during out-of-context synthesis of instance 'e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_input_in\[1\].chdr_to_axis_data_in_in/gen_async_info_fifo.info_fifo_i/fifo_section\[0\].impl_srl_i' at clock pin 'rd_clk' is different from the actual clock period '5.000', this can lead to different synthesis results. WARNING: \[Timing 38-316\] Clock period '10.000' specified during out-of-context synthesis of instance 'e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_input_in\[1\].chdr_to_axis_data_in_in/gen_async_info_fifo.info_fifo_i/fifo_section\[1\].impl_srl_i' at clock pin 'rd_clk' is different from the actual clock period '5.000', this can lead to different synthesis results. WARNING: \[Timing 38-316\] Clock period '10.000' specified during out-of-context synthesis of instance 'e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_input_in\[1\].chdr_to_axis_data_in_in/no_gen_axis_width_conv.gen_async_pyld_fifo.pyld_fifo_i/fifo_section\[0\].impl_srl_i' at clock pin 'rd_clk' is different from the actual clock period '5.000', this can lead to different synthesis results. WARNING: \[Timing 38-316\] Clock period '10.000' specified during out-of-context synthesis of instance 'e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_output_out\[0\].axis_data_to_chdr_out_out/gen_async_info_fifo.pkt_info_fifo/fifo_section\[0\].impl_srl_i' at clock pin 'wr_clk' is different from the actual clock period '5.000', this can lead to different synthesis results. WARNING: \[Timing 38-316\] Clock period '10.000' specified during out-of-context synthesis of instance 'e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_output_out\[0\].axis_data_to_chdr_out_out/gen_async_info_fifo.pkt_info_fifo/fifo_section\[1\].impl_srl_i' at clock pin 'wr_clk' is different from the actual clock period '5.000', this can lead to different synthesis results. WARNING: \[Timing 38-316\] Clock period '10.000' specified during out-of-context synthesis of instance 'e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_output_out\[0\].axis_data_to_chdr_out_out/no_gen_axis_width_conv.gen_async_pyld_fifo.pyld_fifo/fifo_section\[0\].impl_bram_i' at clock pin 'wr_clk' is different from the actual clock period '5.000', this can lead to different synthesis results. WARNING: \[Timing 38-316\] Clock period '10.000' specified during out-of-context synthesis of instance 'e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_output_out\[1\].axis_data_to_chdr_out_out/gen_async_info_fifo.pkt_info_fifo/fifo_section\[0\].impl_srl_i' at clock pin 'wr_clk' is different from the actual clock period '5.000', this can lead to different synthesis results. WARNING: \[Timing 38-316\] Clock period '10.000' specified during out-of-context synthesis of instance 'e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_output_out\[1\].axis_data_to_chdr_out_out/gen_async_info_fifo.pkt_info_fifo/fifo_section\[1\].impl_srl_i' at clock pin 'wr_clk' is different from the actual clock period '5.000', this can lead to different synthesis results. WARNING: \[Timing 38-316\] Clock period '10.000' specified during out-of-context synthesis of instance 'e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_output_out\[1\].axis_data_to_chdr_out_out/no_gen_axis_width_conv.gen_async_pyld_fifo.pyld_fifo/fifo_section\[0\].impl_bram_i' at clock pin 'wr_clk' is different from the actual clock period '5.000', this can lead to different synthesis results. \[00:01:58\] Current task: Synthesis +++ Current Phase: Handling Custom Attributes \[00:03:07\] Current task: Synthesis +++ Current Phase: Loading Part and Timing Information \[00:03:07\] Current task: Synthesis +++ Current Phase: RTL Component Statistics \[00:03:08\] Current task: Synthesis +++ Current Phase: Part Resource Summary WARNING: \[Synth 8-7129\] Port rsta in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port regcea in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port injectsbiterra in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port injectdbiterra in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port clkb in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port regceb in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port web\[0\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[69\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[68\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[67\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[66\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[65\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[64\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[63\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[62\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[61\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[60\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[59\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[58\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[57\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[56\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[55\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[54\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[53\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[52\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[51\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[50\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[49\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[48\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[47\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[46\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[45\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[44\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[43\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[42\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[41\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[40\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[39\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[38\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[37\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[36\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[35\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[34\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[33\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[32\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[31\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[30\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[29\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[28\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[27\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[26\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[25\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[24\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[23\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[22\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[21\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[20\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[19\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[18\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[17\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[16\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[15\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[14\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[13\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[12\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[11\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[10\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[9\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[8\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[7\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[6\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[5\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[4\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[3\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[2\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[1\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[0\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port injectsbiterrb in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port injectdbiterrb in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port s_sc_req\[0\] in module sc_node_v1_0_13_top__parameterized3 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port s_sc_info\[0\] in module sc_node_v1_0_13_top__parameterized3 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port s_sc_payld\[0\] in module sc_node_v1_0_13_top__parameterized3 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port m_sc_aclken in module sc_node_v1_0_13_top__parameterized3 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port m_axis_arb_tready in module sc_node_v1_0_13_top__parameterized3 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port s_axis_arb_tvalid in module sc_node_v1_0_13_top__parameterized3 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port s_axis_arb_tdata\[15\] in module sc_node_v1_0_13_top__parameterized3 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port s_axis_arb_tdata\[14\] in module sc_node_v1_0_13_top__parameterized3 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port s_axis_arb_tdata\[13\] in module sc_node_v1_0_13_top__parameterized3 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port s_axis_arb_tdata\[12\] in module sc_node_v1_0_13_top__parameterized3 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port s_axis_arb_tdata\[11\] in module sc_node_v1_0_13_top__parameterized3 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port s_axis_arb_tdata\[10\] in module sc_node_v1_0_13_top__parameterized3 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port s_axis_arb_tdata\[9\] in module sc_node_v1_0_13_top__parameterized3 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port s_axis_arb_tdata\[8\] in module sc_node_v1_0_13_top__parameterized3 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port s_axis_arb_tdata\[7\] in module sc_node_v1_0_13_top__parameterized3 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port s_axis_arb_tdata\[6\] in module sc_node_v1_0_13_top__parameterized3 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port s_axis_arb_tdata\[5\] in module sc_node_v1_0_13_top__parameterized3 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port s_axis_arb_tdata\[4\] in module sc_node_v1_0_13_top__parameterized3 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port s_axis_arb_tdata\[3\] in module sc_node_v1_0_13_top__parameterized3 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port s_axis_arb_tdata\[2\] in module sc_node_v1_0_13_top__parameterized3 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port s_axis_arb_tdata\[1\] in module sc_node_v1_0_13_top__parameterized3 is either unconnected or has no load WARNING: \[Synth 8-6014\] Unused sequential element ingress_fifo_i/main_fifo/fifo_bram/ram/impl/ram_reg was removed. WARNING: \[Synth 8-6014\] Unused sequential element ingress_fifo_i/main_fifo/fifo_bram/ram/impl/ram_reg was removed. WARNING: \[Synth 8-6014\] Unused sequential element ingress_fifo_i/main_fifo/fifo_bram/ram/impl/ram_reg was removed. WARNING: \[Synth 8-6014\] Unused sequential element ingress_fifo_i/main_fifo/fifo_bram/ram/impl/ram_reg was removed. WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awid\[1\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awid\[0\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awsize\[5\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awsize\[4\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awsize\[3\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awsize\[2\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awsize\[1\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awsize\[0\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awburst\[3\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awburst\[2\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awburst\[1\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awburst\[0\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awlock\[1\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awlock\[0\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awcache\[7\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awcache\[6\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awcache\[5\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awcache\[4\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awcache\[3\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awcache\[2\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awcache\[1\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awcache\[0\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awprot\[5\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awprot\[4\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awprot\[3\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awprot\[2\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awprot\[1\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awprot\[0\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awqos\[7\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awqos\[6\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awqos\[5\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awqos\[4\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awqos\[3\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awqos\[2\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awqos\[1\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awqos\[0\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awregion\[7\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awregion\[6\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awregion\[5\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awregion\[4\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awregion\[3\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awregion\[2\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awregion\[1\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awregion\[0\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awuser\[1\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awuser\[0\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_wstrb\[15\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_wstrb\[14\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_wstrb\[13\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_wstrb\[12\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_wstrb\[11\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_wstrb\[10\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_wstrb\[9\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_wstrb\[8\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_wstrb\[7\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_wstrb\[6\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_wstrb\[5\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_wstrb\[4\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_wstrb\[3\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_wstrb\[2\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_wstrb\[1\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_wstrb\[0\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_wuser\[1\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_wuser\[0\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arid\[1\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arid\[0\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arsize\[5\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arsize\[4\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arsize\[3\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arsize\[2\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arsize\[1\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arsize\[0\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arburst\[3\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arburst\[2\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arburst\[1\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arburst\[0\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arlock\[1\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arlock\[0\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arcache\[7\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arcache\[6\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arcache\[5\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arcache\[4\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arcache\[3\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arcache\[2\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arcache\[1\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arcache\[0\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arprot\[5\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arprot\[4\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arprot\[3\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arprot\[2\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arprot\[1\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arprot\[0\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arqos\[7\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arqos\[6\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arqos\[5\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arqos\[4\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arqos\[3\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arqos\[2\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arqos\[1\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arqos\[0\] driven by constant 0 WARNING: \[Synth 8-6014\] Unused sequential element rec_axi_fifo/fifo_bram/ram/impl/ram_reg was removed. WARNING: \[Synth 8-6014\] Unused sequential element play_axi_fifo/fifo_bram/ram/impl/ram_reg was removed. WARNING: \[Synth 8-6014\] Unused sequential element rec_axi_fifo/fifo_bram/ram/impl/ram_reg was removed. WARNING: \[Synth 8-6014\] Unused sequential element play_axi_fifo/fifo_bram/ram/impl/ram_reg was removed. WARNING: \[Synth 8-6014\] Unused sequential element no_gen_axis_width_conv.gen_async_pyld_fifo.pyld_fifo/ext_fifo_i/ram/impl/ram_reg was removed. WARNING: \[Synth 8-6014\] Unused sequential element no_gen_axis_width_conv.gen_async_pyld_fifo.pyld_fifo/ext_fifo_i/ram/impl/ram_reg was removed. WARNING: \[Synth 8-6014\] Unused sequential element gen_ctrl_slave.axis_ctrl_slv_i/gate_i/ram_i/impl/ram_reg was removed. WARNING: \[Synth 8-3936\] Found unconnected internal register 'ctrlport_timer_i/resp_cache_i/o_tdata_reg' and it is trimmed from '34' to '32' bits. \[/home/grcusrp/uhd/fpga/usrp3/lib/fifo/axi_fifo_flop.v:37\] WARNING: \[Synth 8-6014\] Unused sequential element gen_axis_width_conv.pyld_fifo_i/fifo_bram/ram/impl/ram_reg was removed. WARNING: \[Synth 8-6014\] Unused sequential element gen_axis_width_conv.pyld_fifo_i/fifo_bram/ram/impl/ram_reg was removed. WARNING: \[Synth 8-6014\] Unused sequential element gen_axis_width_conv.pyld_fifo/fifo_bram/ram/impl/ram_reg was removed. WARNING: \[Synth 8-6014\] Unused sequential element gen_axis_width_conv.pyld_fifo/fifo_bram/ram/impl/ram_reg was removed. WARNING: \[Synth 8-6014\] Unused sequential element gen_ctrl_slave.slv_fifo_i/fifo_bram/ram/impl/ram_reg was removed. WARNING: \[Synth 8-6014\] Unused sequential element gen_ctrl_slave.axis_ctrl_slv_i/gate_i/ram_i/impl/ram_reg was removed. WARNING: \[Synth 8-3936\] Found unconnected internal register 'dest_mux_i/axi_fifo/fifo_flop2/o_tdata_reg' and it is trimmed from '5' to '4' bits. \[/home/grcusrp/uhd/fpga/usrp3/lib/fifo/axi_fifo_flop2.v:38\] WARNING: \[Synth 8-3936\] Found unconnected internal register 'dest_mux_i/axi_fifo/fifo_flop2/o_tdata_reg' and it is trimmed from '5' to '4' bits. \[/home/grcusrp/uhd/fpga/usrp3/lib/fifo/axi_fifo_flop2.v:38\] WARNING: \[Synth 8-3936\] Found unconnected internal register 'dest_mux_i/axi_fifo/fifo_flop2/o_tdata_reg' and it is trimmed from '5' to '4' bits. \[/home/grcusrp/uhd/fpga/usrp3/lib/fifo/axi_fifo_flop2.v:38\] WARNING: \[Synth 8-3936\] Found unconnected internal register 'dest_mux_i/axi_fifo/fifo_flop2/o_tdata_reg' and it is trimmed from '5' to '4' bits. \[/home/grcusrp/uhd/fpga/usrp3/lib/fifo/axi_fifo_flop2.v:38\] WARNING: \[Synth 8-3936\] Found unconnected internal register 'dest_mux_i/axi_fifo/fifo_flop2/o_tdata_reg' and it is trimmed from '5' to '4' bits. \[/home/grcusrp/uhd/fpga/usrp3/lib/fifo/axi_fifo_flop2.v:38\] WARNING: \[Synth 8-6014\] Unused sequential element axi_packet_gate_i/ram_i/impl/ram_reg was removed. WARNING: \[Synth 8-6014\] Unused sequential element axi_packet_gate_i/ram_i/impl/ram_reg was removed. WARNING: \[Synth 8-6014\] Unused sequential element axi_packet_gate_i/ram_i/impl/ram_reg was removed. WARNING: \[Synth 8-6014\] Unused sequential element axi_packet_gate_i/ram_i/impl/ram_reg was removed. WARNING: \[Synth 8-6014\] Unused sequential element axi_packet_gate_i/ram_i/impl/ram_reg was removed. WARNING: \[Synth 8-6014\] Unused sequential element kv_map_i/map_i/mem_i/impl/ram_reg was removed. WARNING: \[Synth 8-3936\] Found unconnected internal register 'ppslp/coarse_reg' and it is trimmed from '28' to '16' bits. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/ppsloop.v:243\] WARNING: \[Synth 8-6014\] Unused sequential element cpu_out_gate_i/ram_i/impl/ram_reg was removed. WARNING: \[Synth 8-6014\] Unused sequential element chdr_user_fifo_i/fifo_bram/ram/impl/ram_reg was removed. WARNING: \[Synth 8-6014\] Unused sequential element chdr_out_gate_i/ram_i/impl/ram_reg was removed. WARNING: \[Synth 8-6014\] Unused sequential element chdr_out_gate_i/addr_fifo_i/fifo_bram/ram/impl/ram_reg was removed. WARNING: \[Synth 8-6014\] Unused sequential element kv_map_i/mem_i/impl/ram_reg was removed. WARNING: \[Synth 8-6014\] Unused sequential element eth_adapter_i/cpu_fifo_i/fifo_bram/ram/impl/ram_reg was removed. WARNING: \[Synth 8-6014\] Unused sequential element eth_adapter_i/chdr_fifo_i/fifo_bram/ram/impl/ram_reg was removed. WARNING: \[Synth 8-6014\] Unused sequential element inst_axi_pmu/axi_fifo_short_inst/ram/impl/ram_reg was removed. \[00:04:45\] Current task: Synthesis +++ Current Phase: Cross Boundary and Area Optimization \[00:04:51\] Current task: Synthesis +++ Current Phase: Applying XDC Timing Constraints \[00:05:41\] Current task: Synthesis +++ Current Phase: Timing Optimization \[00:06:26\] Current task: Synthesis +++ Current Phase: Technology Mapping \[00:06:26\] Current task: Synthesis +++ Current Phase: IO Insertion \[00:06:29\] Current task: Synthesis +++ Current Phase: Flattening Before IO Insertion WARNING: \[Synth 8-3295\] tying undriven pin I_AXI_DMA_REG_MODULE/strm_valid_int2_inferred:in0 to constant 0 WARNING: \[Synth 8-3295\] tying undriven pin I_AXI_DMA_REG_MODULE/strm_valid_int_cdc_to_inferred:in0 to constant 0 \[00:06:44\] Current task: Synthesis +++ Current Phase: Final Netlist Cleanup WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/ipshared/7ee4/hdl/axi_clock_converter_v2_1_vl_rfs.v:543\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/ipshared/7ee4/hdl/axi_clock_converter_v2_1_vl_rfs.v:555\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/ipshared/7ee4/hdl/axi_clock_converter_v2_1_vl_rfs.v:544\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/ipshared/7ee4/hdl/axi_clock_converter_v2_1_vl_rfs.v:599\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/ipshared/7ee4/hdl/axi_clock_converter_v2_1_vl_rfs.v:544\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/ipshared/7ee4/hdl/axi_clock_converter_v2_1_vl_rfs.v:556\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/ipshared/7ee4/hdl/axi_clock_converter_v2_1_vl_rfs.v:556\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:583\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:221\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:221\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:221\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/ipshared/7ee4/hdl/axi_clock_converter_v2_1_vl_rfs.v:600\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/ipshared/7ee4/hdl/axi_clock_converter_v2_1_vl_rfs.v:600\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:594\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:221\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:221\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:221\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:594\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:221\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:221\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:221\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/ipshared/7ee4/hdl/axi_clock_converter_v2_1_vl_rfs.v:600\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/ipshared/7ee4/hdl/axi_clock_converter_v2_1_vl_rfs.v:600\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:594\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:221\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:221\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:221\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/ipshared/7ee4/hdl/axi_clock_converter_v2_1_vl_rfs.v:600\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/ipshared/7ee4/hdl/axi_clock_converter_v2_1_vl_rfs.v:600\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:583\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:221\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:221\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:221\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:588\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:588\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:588\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:588\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:588\] \[00:06:54\] Current task: Synthesis +++ Current Phase: Renaming Generated Instances \[00:07:02\] Current task: Synthesis +++ Current Phase: Rebuilding User Hierarchy \[00:07:06\] Current task: Synthesis +++ Current Phase: Renaming Generated Ports \[00:07:06\] Current task: Synthesis +++ Current Phase: Handling Custom Attributes \[00:07:07\] Current task: Synthesis +++ Current Phase: Renaming Generated Nets \[00:07:11\] Current task: Synthesis +++ Current Phase: Writing Synthesis Report \[00:07:11\] Current task: Synthesis +++ Current Phase: Finished \[00:07:11\] Translating Synthesized Netlist CRITICAL WARNING: \[Designutils 20-1280\] Could not find module 'axi_hb31'. The XDC file /home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_hb31/constraints/fir_compiler_v7_2.xdc will not be read for any cell of this module. CRITICAL WARNING: \[Designutils 20-1280\] Could not find module 'axi_hb47'. The XDC file /home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_hb47/constraints/fir_compiler_v7_2.xdc will not be read for any cell of this module. WARNING: \[Vivado_Tcl 4-919\] Waiver ID 'CDC-1' -from list should not be empty. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_axi_dma_eth_internal_0/e31x_ps_bd_axi_dma_eth_internal_0.xdc:61\] CRITICAL WARNING: \[Netlist 29-160\] Cannot set property 'iostandard', because the property does not exist for objects of type 'pin'. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/e31x_ps_bd_processing_system7_0_0.xdc:405\] CRITICAL WARNING: \[Netlist 29-160\] Cannot set property 'PACKAGE_PIN', because the property does not exist for objects of type 'pin'. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/e31x_ps_bd_processing_system7_0_0.xdc:406\] CRITICAL WARNING: \[Netlist 29-160\] Cannot set property 'slew', because the property does not exist for objects of type 'pin'. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/e31x_ps_bd_processing_system7_0_0.xdc:407\] CRITICAL WARNING: \[Netlist 29-160\] Cannot set property 'PIO_DIRECTION', because the property does not exist for objects of type 'pin'. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/e31x_ps_bd_processing_system7_0_0.xdc:408\] CRITICAL WARNING: \[Netlist 29-160\] Cannot set property 'iostandard', because the property does not exist for objects of type 'pin'. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/e31x_ps_bd_processing_system7_0_0.xdc:417\] CRITICAL WARNING: \[Netlist 29-160\] Cannot set property 'PACKAGE_PIN', because the property does not exist for objects of type 'pin'. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/e31x_ps_bd_processing_system7_0_0.xdc:418\] CRITICAL WARNING: \[Netlist 29-160\] Cannot set property 'slew', because the property does not exist for objects of type 'pin'. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/e31x_ps_bd_processing_system7_0_0.xdc:419\] CRITICAL WARNING: \[Netlist 29-160\] Cannot set property 'PIO_DIRECTION', because the property does not exist for objects of type 'pin'. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/e31x_ps_bd_processing_system7_0_0.xdc:420\] WARNING: \[Vivado 12-4702\] slew is not a supported property on input port(s). Setting is ignored. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/e31x_ps_bd_processing_system7_0_0.xdc:691\] WARNING: \[Vivado 12-4702\] slew is not a supported property on input port(s). Setting is ignored. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/e31x_ps_bd_processing_system7_0_0.xdc:694\] WARNING: \[Vivado 12-4702\] slew is not a supported property on input port(s). Setting is ignored. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/e31x_ps_bd_processing_system7_0_0.xdc:697\] CRITICAL WARNING: \[Constraints 18-1055\] Clock 'bus_clk' completely overrides clock 'clk_fpga_0', which is referenced by one or more other constraints. Any constraints that refer to the overridden clock will be ignored. CRITICAL WARNING: \[Constraints 18-1055\] Clock 'clk40' completely overrides clock 'clk_fpga_1', which is referenced by one or more other constraints. Any constraints that refer to the overridden clock will be ignored. WARNING: \[Vivado 12-2489\] -input_jitter contains time 1.628100 which will be rounded to 1.628 to ensure it is an integer multiple of 1 picosecond \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_timing.xdc:47\] WARNING: \[Vivado 12-830\] No fanout objects found for 'all_fanout -from \[get_ports -scoped_to_current_instance m_axi_aclk\] -flat -endpoints_only -only_cells'. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_auto_cc_4/e31x_ps_bd_auto_cc_4_clocks.xdc:17\] WARNING: \[Vivado_Tcl 4-921\] Waiver ID 'CDC-10' -to list should not be empty. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_auto_cc_0/e31x_ps_bd_auto_cc_0_clocks.xdc:7\] WARNING: \[Vivado_Tcl 4-921\] Waiver ID 'CDC-11' -to list should not be empty. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_auto_cc_0/e31x_ps_bd_auto_cc_0_clocks.xdc:10\] WARNING: \[Vivado_Tcl 4-921\] Waiver ID 'CDC-15' -to list should not be empty. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_auto_cc_0/e31x_ps_bd_auto_cc_0_clocks.xdc:13\] WARNING: \[Vivado_Tcl 4-939\] Waiver ID 'LUTAR-1' object list should not be empty (perhaps an invalid wildcard was used or only unsupported objects). \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_auto_cc_0/e31x_ps_bd_auto_cc_0_clocks.xdc:17\] WARNING: \[Vivado_Tcl 4-921\] Waiver ID 'CDC-10' -to list should not be empty. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_auto_cc_1/e31x_ps_bd_auto_cc_1_clocks.xdc:7\] WARNING: \[Vivado_Tcl 4-921\] Waiver ID 'CDC-11' -to list should not be empty. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_auto_cc_1/e31x_ps_bd_auto_cc_1_clocks.xdc:10\] WARNING: \[Vivado_Tcl 4-921\] Waiver ID 'CDC-15' -to list should not be empty. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_auto_cc_1/e31x_ps_bd_auto_cc_1_clocks.xdc:13\] WARNING: \[Vivado_Tcl 4-939\] Waiver ID 'LUTAR-1' object list should not be empty (perhaps an invalid wildcard was used or only unsupported objects). \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_auto_cc_1/e31x_ps_bd_auto_cc_1_clocks.xdc:17\] WARNING: \[Vivado_Tcl 4-921\] Waiver ID 'CDC-10' -to list should not be empty. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_auto_cc_2/e31x_ps_bd_auto_cc_2_clocks.xdc:7\] WARNING: \[Vivado_Tcl 4-921\] Waiver ID 'CDC-11' -to list should not be empty. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_auto_cc_2/e31x_ps_bd_auto_cc_2_clocks.xdc:10\] WARNING: \[Vivado_Tcl 4-921\] Waiver ID 'CDC-15' -to list should not be empty. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_auto_cc_2/e31x_ps_bd_auto_cc_2_clocks.xdc:13\] WARNING: \[Vivado_Tcl 4-939\] Waiver ID 'LUTAR-1' object list should not be empty (perhaps an invalid wildcard was used or only unsupported objects). \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_auto_cc_2/e31x_ps_bd_auto_cc_2_clocks.xdc:17\] WARNING: \[Vivado_Tcl 4-921\] Waiver ID 'CDC-10' -to list should not be empty. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_auto_cc_3/e31x_ps_bd_auto_cc_3_clocks.xdc:7\] WARNING: \[Vivado_Tcl 4-921\] Waiver ID 'CDC-11' -to list should not be empty. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_auto_cc_3/e31x_ps_bd_auto_cc_3_clocks.xdc:10\] WARNING: \[Vivado_Tcl 4-921\] Waiver ID 'CDC-15' -to list should not be empty. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_auto_cc_3/e31x_ps_bd_auto_cc_3_clocks.xdc:13\] WARNING: \[Vivado_Tcl 4-939\] Waiver ID 'LUTAR-1' object list should not be empty (perhaps an invalid wildcard was used or only unsupported objects). \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_auto_cc_3/e31x_ps_bd_auto_cc_3_clocks.xdc:17\] WARNING: \[XPM_CDC_GRAY: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_GRAY: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_GRAY: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_GRAY: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_GRAY: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_GRAY: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_GRAY: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_GRAY: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_GRAY: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_GRAY: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[Vivado_Tcl 4-919\] Waiver ID 'CDC-15' -from list should not be empty. \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl:30\] WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[Vivado_Tcl 4-919\] Waiver ID 'CDC-15' -from list should not be empty. \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl:30\] WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[Vivado_Tcl 4-919\] Waiver ID 'CDC-15' -from list should not be empty. \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl:30\] WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[0\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[10\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[11\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[12\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[13\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[14\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[15\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[16\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[17\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[18\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[19\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[1\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[20\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[21\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[22\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[23\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[24\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[25\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[26\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[27\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[28\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[29\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[2\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[30\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[31\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[3\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[4\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[5\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[6\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[7\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[8\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[9\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[0\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[16\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[17\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[18\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[19\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[1\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[20\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[21\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[22\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[23\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[24\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[25\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[26\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[27\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[28\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[29\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[2\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[30\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[31\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[0\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[10\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[11\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[12\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[13\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[14\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[15\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[16\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[17\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[18\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[19\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[1\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[20\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[21\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[22\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[23\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[24\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[25\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[26\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[27\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[28\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[29\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[2\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[30\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[31\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[3\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[4\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[5\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[6\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[7\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[8\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[9\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_out_iob_reg\[0\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_out_iob_reg\[16\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_out_iob_reg\[17\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_out_iob_reg\[18\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_out_iob_reg\[19\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_out_iob_reg\[1\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_out_iob_reg\[20\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_out_iob_reg\[21\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_out_iob_reg\[22\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_out_iob_reg\[23\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_out_iob_reg\[24\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_out_iob_reg\[25\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_out_iob_reg\[26\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_out_iob_reg\[27\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_out_iob_reg\[28\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_out_iob_reg\[29\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_out_iob_reg\[2\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. \[00:08:33\] Current task: Translating Synthesized Netlist +++ Current Phase: Starting \[00:08:33\] Current task: Translating Synthesized Netlist +++ Current Phase: Finished \[00:08:33\] Executing Tcl: report_drc -ruledeck methodology_checks -file /home/grcusrp/uhd/fpga/usrp3/top/e31x/build-E310_SG3/methodology.rpt \[00:08:33\] Starting DRC Command \[00:09:16\] Current task: DRC +++ Current Phase: Starting \[00:09:17\] Current task: DRC +++ Current Phase: Finished \[00:09:17\] Executing Tcl: opt_design -directive Default \[00:09:17\] Starting Logic Optimization Command \[00:09:17\] Current task: Logic Optimization +++ Current Phase: Starting \[00:09:17\] Current task: Logic Optimization +++ Current Phase: Finished \[00:09:17\] Starting DRC Task \[00:09:18\] Current task: DRC +++ Current Phase: Starting \[00:09:18\] Current task: DRC +++ Current Phase: Finished \[00:09:18\] Starting Cache Timing Information Task \[00:09:26\] Current task: Cache Timing Information +++ Current Phase: Starting \[00:09:26\] Current task: Cache Timing Information +++ Current Phase: Finished \[00:09:26\] Starting Logic Optimization Task \[00:09:31\] Current task: Logic Optimization +++ Current Phase: Starting \[00:09:33\] Current task: Logic Optimization +++ Current Phase: 1 Retarget \[00:09:34\] Current task: Logic Optimization +++ Current Phase: 2 Constant propagation \[00:09:40\] Current task: Logic Optimization +++ Current Phase: 3 Sweep \[00:09:42\] Current task: Logic Optimization +++ Current Phase: 4 BUFG optimization \[00:09:42\] Current task: Logic Optimization +++ Current Phase: 5 Shift Register Optimization \[00:09:44\] Current task: Logic Optimization +++ Current Phase: 6 Post Processing Netlist \[00:09:45\] Current task: Logic Optimization +++ Current Phase: Finished \[00:09:45\] Starting Connectivity Check Task \[00:09:45\] Current task: Connectivity Check +++ Current Phase: Starting \[00:09:46\] Current task: Connectivity Check +++ Current Phase: Finished \[00:09:46\] Starting Power Optimization Task \[00:10:09\] Current task: Power Optimization +++ Current Phase: Starting \[00:10:10\] Current task: Power Optimization +++ Current Phase: Finished \[00:10:10\] Starting PowerOpt Patch Enables Task \[00:10:10\] Current task: PowerOpt Patch Enables +++ Current Phase: Starting \[00:10:11\] Current task: PowerOpt Patch Enables +++ Current Phase: Finished \[00:10:11\] Starting Final Cleanup Task \[00:10:12\] Current task: Final Cleanup +++ Current Phase: Starting \[00:10:13\] Current task: Final Cleanup +++ Current Phase: Finished \[00:10:13\] Starting Logic Optimization Task \[00:10:24\] Current task: Logic Optimization +++ Current Phase: Starting \[00:10:24\] Current task: Logic Optimization +++ Current Phase: Finished \[00:10:24\] Starting Netlist Obfuscation Task \[00:10:24\] Current task: Netlist Obfuscation +++ Current Phase: Starting \[00:10:24\] Current task: Netlist Obfuscation +++ Current Phase: Finished \[00:10:24\] Executing Tcl: place_design -directive Default \[00:10:24\] Starting Placer Command \[00:10:42\] Current task: Placer +++ Current Phase: Starting WARNING: \[DRC CHECK-3\] Report rule limit reached: REQP-1839 rule limit reached: 20 violations have been found. WARNING: \[DRC REQP-1839\] RAMB36 async control check: The RAMB36E1 e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_input_in\[0\].chdr_to_axis_data_in_in/gen_axis_width_conv.pyld_fifo_i/fifo_bram/ram/impl/ram_reg_0 has an input control pin e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_input_in\[0\].chdr_to_axis_data_in_in/gen_axis_width_conv.pyld_fifo_i/fifo_bram/ram/impl/ram_reg_0/ENBWREN (net: e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_input_in\[0\].chdr_to_axis_data_in_in/gen_axis_width_conv.pyld_fifo_i/fifo_bram/ram/impl/enb0) which is driven by a register (e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_input_in\[0\].chdr_to_axis_data_in_in/gen_axis_width_conv.payload_width_conv_i/fifo_i/fifo_section\[0\].impl_srl_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: \[DRC REQP-1839\] RAMB36 async control check: The RAMB36E1 e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_input_in\[0\].chdr_to_axis_data_in_in/gen_axis_width_conv.pyld_fifo_i/fifo_bram/ram/impl/ram_reg_1 has an input control pin e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_input_in\[0\].chdr_to_axis_data_in_in/gen_axis_width_conv.pyld_fifo_i/fifo_bram/ram/impl/ram_reg_1/ENBWREN (net: e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_input_in\[0\].chdr_to_axis_data_in_in/gen_axis_width_conv.pyld_fifo_i/fifo_bram/ram/impl/enb0) which is driven by a register (e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_input_in\[0\].chdr_to_axis_data_in_in/gen_axis_width_conv.payload_width_conv_i/fifo_i/fifo_section\[0\].impl_srl_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: \[DRC REQP-1839\] RAMB36 async control check: The RAMB36E1 e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_input_in\[1\].chdr_to_axis_data_in_in/gen_axis_width_conv.pyld_fifo_i/fifo_bram/ram/impl/ram_reg_0 has an input control pin e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_input_in\[1\].chdr_to_axis_data_in_in/gen_axis_width_conv.pyld_fifo_i/fifo_bram/ram/impl/ram_reg_0/ENBWREN (net: e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_input_in\[1\].chdr_to_axis_data_in_in/gen_axis_width_conv.pyld_fifo_i/fifo_bram/ram/impl/enb0) which is driven by a register (e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_input_in\[1\].chdr_to_axis_data_in_in/gen_axis_width_conv.payload_width_conv_i/fifo_i/fifo_section\[0\].impl_srl_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: \[DRC REQP-1839\] RAMB36 async control check: The RAMB36E1 e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_input_in\[1\].chdr_to_axis_data_in_in/gen_axis_width_conv.pyld_fifo_i/fifo_bram/ram/impl/ram_reg_1 has an input control pin e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_input_in\[1\].chdr_to_axis_data_in_in/gen_axis_width_conv.pyld_fifo_i/fifo_bram/ram/impl/ram_reg_1/ENBWREN (net: e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_input_in\[1\].chdr_to_axis_data_in_in/gen_axis_width_conv.pyld_fifo_i/fifo_bram/ram/impl/enb0) which is driven by a register (e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_input_in\[1\].chdr_to_axis_data_in_in/gen_axis_width_conv.payload_width_conv_i/fifo_i/fifo_section\[0\].impl_srl_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: \[DRC REQP-1839\] RAMB36 async control check: The RAMB36E1 e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_output_out\[0\].axis_data_to_chdr_out_out/gen_axis_width_conv.pyld_fifo/fifo_bram/ram/impl/ram_reg_0 has an input control pin e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_output_out\[0\].axis_data_to_chdr_out_out/gen_axis_width_conv.pyld_fifo/fifo_bram/ram/impl/ram_reg_0/ENARDEN (net: e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_output_out\[0\].axis_data_to_chdr_out_out/gen_axis_width_conv.pyld_fifo/fifo_bram/ram/impl/E\[0\]) which is driven by a register (e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_output_out\[0\].axis_data_to_chdr_out_out/gen_axis_width_conv.payload_width_conv_i/fifo_i/fifo_section\[0\].impl_srl_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: \[DRC REQP-1839\] RAMB36 async control check: The RAMB36E1 e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_output_out\[0\].axis_data_to_chdr_out_out/gen_axis_width_conv.pyld_fifo/fifo_bram/ram/impl/ram_reg_1 has an input control pin e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_output_out\[0\].axis_data_to_chdr_out_out/gen_axis_width_conv.pyld_fifo/fifo_bram/ram/impl/ram_reg_1/ENARDEN (net: e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_output_out\[0\].axis_data_to_chdr_out_out/gen_axis_width_conv.pyld_fifo/fifo_bram/ram/impl/E\[0\]) which is driven by a register (e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_output_out\[0\].axis_data_to_chdr_out_out/gen_axis_width_conv.payload_width_conv_i/fifo_i/fifo_section\[0\].impl_srl_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: \[DRC REQP-1839\] RAMB36 async control check: The RAMB36E1 e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_output_out\[0\].axis_data_to_chdr_out_out/gen_axis_width_conv.pyld_fifo/fifo_bram/ram/impl/ram_reg_2 has an input control pin e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_output_out\[0\].axis_data_to_chdr_out_out/gen_axis_width_conv.pyld_fifo/fifo_bram/ram/impl/ram_reg_2/ENARDEN (net: e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_output_out\[0\].axis_data_to_chdr_out_out/gen_axis_width_conv.pyld_fifo/fifo_bram/ram/impl/E\[0\]) which is driven by a register (e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_output_out\[0\].axis_data_to_chdr_out_out/gen_axis_width_conv.payload_width_conv_i/fifo_i/fifo_section\[0\].impl_srl_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: \[DRC REQP-1839\] RAMB36 async control check: The RAMB36E1 e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_output_out\[0\].axis_data_to_chdr_out_out/gen_axis_width_conv.pyld_fifo/fifo_bram/ram/impl/ram_reg_3 has an input control pin e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_output_out\[0\].axis_data_to_chdr_out_out/gen_axis_width_conv.pyld_fifo/fifo_bram/ram/impl/ram_reg_3/ENARDEN (net: e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_output_out\[0\].axis_data_to_chdr_out_out/gen_axis_width_conv.pyld_fifo/fifo_bram/ram/impl/E\[0\]) which is driven by a register (e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_output_out\[0\].axis_data_to_chdr_out_out/gen_axis_width_conv.payload_width_conv_i/fifo_i/fifo_section\[0\].impl_srl_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: \[DRC REQP-1839\] RAMB36 async control check: The RAMB36E1 e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_output_out\[1\].axis_data_to_chdr_out_out/gen_axis_width_conv.pyld_fifo/fifo_bram/ram/impl/ram_reg_0 has an input control pin e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_output_out\[1\].axis_data_to_chdr_out_out/gen_axis_width_conv.pyld_fifo/fifo_bram/ram/impl/ram_reg_0/ENARDEN (net: e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_output_out\[1\].axis_data_to_chdr_out_out/gen_axis_width_conv.pyld_fifo/fifo_bram/ram/impl/E\[0\]) which is driven by a register (e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_output_out\[1\].axis_data_to_chdr_out_out/gen_axis_width_conv.payload_width_conv_i/fifo_i/fifo_section\[0\].impl_srl_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: \[DRC REQP-1839\] RAMB36 async control check: The RAMB36E1 e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_output_out\[1\].axis_data_to_chdr_out_out/gen_axis_width_conv.pyld_fifo/fifo_bram/ram/impl/ram_reg_1 has an input control pin e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_output_out\[1\].axis_data_to_chdr_out_out/gen_axis_width_conv.pyld_fifo/fifo_bram/ram/impl/ram_reg_1/ENARDEN (net: e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_output_out\[1\].axis_data_to_chdr_out_out/gen_axis_width_conv.pyld_fifo/fifo_bram/ram/impl/E\[0\]) which is driven by a register (e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_output_out\[1\].axis_data_to_chdr_out_out/gen_axis_width_conv.payload_width_conv_i/fifo_i/fifo_section\[0\].impl_srl_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: \[DRC REQP-1839\] RAMB36 async control check: The RAMB36E1 e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_output_out\[1\].axis_data_to_chdr_out_out/gen_axis_width_conv.pyld_fifo/fifo_bram/ram/impl/ram_reg_2 has an input control pin e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_output_out\[1\].axis_data_to_chdr_out_out/gen_axis_width_conv.pyld_fifo/fifo_bram/ram/impl/ram_reg_2/ENARDEN (net: e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_output_out\[1\].axis_data_to_chdr_out_out/gen_axis_width_conv.pyld_fifo/fifo_bram/ram/impl/E\[0\]) which is driven by a register (e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_output_out\[1\].axis_data_to_chdr_out_out/gen_axis_width_conv.payload_width_conv_i/fifo_i/fifo_section\[0\].impl_srl_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: \[DRC REQP-1839\] RAMB36 async control check: The RAMB36E1 e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_output_out\[1\].axis_data_to_chdr_out_out/gen_axis_width_conv.pyld_fifo/fifo_bram/ram/impl/ram_reg_3 has an input control pin e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_output_out\[1\].axis_data_to_chdr_out_out/gen_axis_width_conv.pyld_fifo/fifo_bram/ram/impl/ram_reg_3/ENARDEN (net: e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_output_out\[1\].axis_data_to_chdr_out_out/gen_axis_width_conv.pyld_fifo/fifo_bram/ram/impl/E\[0\]) which is driven by a register (e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_output_out\[1\].axis_data_to_chdr_out_out/gen_axis_width_conv.payload_width_conv_i/fifo_i/fifo_section\[0\].impl_srl_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: \[DRC REQP-1839\] RAMB36 async control check: The RAMB36E1 e31x_core_inst/rfnoc_image_core_i/b_replay0_1/gen_replay_blocks\[0\].axis_replay_i/play_axi_fifo/fifo_bram/ram/impl/ram_reg has an input control pin e31x_core_inst/rfnoc_image_core_i/b_replay0_1/gen_replay_blocks\[0\].axis_replay_i/play_axi_fifo/fifo_bram/ram/impl/ram_reg/ENARDEN (net: e31x_core_inst/rfnoc_image_core_i/b_replay0_1/gen_replay_blocks\[0\].axis_replay_i/play_axi_fifo/fifo_bram/ram/impl/enb0) which is driven by a register (e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_output_out\[0\].axis_data_to_chdr_out_out/no_gen_axis_width_conv.gen_async_pyld_fifo.pyld_fifo/fifo_section\[0\].impl_bram_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: \[DRC REQP-1839\] RAMB36 async control check: The RAMB36E1 e31x_core_inst/rfnoc_image_core_i/b_replay0_1/gen_replay_blocks\[1\].axis_replay_i/play_axi_fifo/fifo_bram/ram/impl/ram_reg has an input control pin e31x_core_inst/rfnoc_image_core_i/b_replay0_1/gen_replay_blocks\[1\].axis_replay_i/play_axi_fifo/fifo_bram/ram/impl/ram_reg/ENARDEN (net: e31x_core_inst/rfnoc_image_core_i/b_replay0_1/gen_replay_blocks\[1\].axis_replay_i/play_axi_fifo/fifo_bram/ram/impl/enb0) which is driven by a register (e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_output_out\[1\].axis_data_to_chdr_out_out/no_gen_axis_width_conv.gen_async_pyld_fifo.pyld_fifo/fifo_section\[0\].impl_bram_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: \[DRC REQP-1839\] RAMB36 async control check: The RAMB36E1 e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_output_out\[0\].axis_data_to_chdr_out_out/no_gen_axis_width_conv.gen_async_pyld_fifo.pyld_fifo/fifo_section\[0\].impl_bram_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop\[0\].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram has an input control pin e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_output_out\[0\].axis_data_to_chdr_out_out/no_gen_axis_width_conv.gen_async_pyld_fifo.pyld_fifo/fifo_section\[0\].impl_bram_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop\[0\].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram/ADDRARDADDR\[10\] (net: e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_output_out\[0\].axis_data_to_chdr_out_out/no_gen_axis_width_conv.gen_async_pyld_fifo.pyld_fifo/fifo_section\[0\].impl_bram_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop\[0\].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_0\[4\]) which is driven by a register (e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_output_out\[0\].axis_data_to_chdr_out_out/no_gen_axis_width_conv.gen_async_pyld_fifo.pyld_fifo/fifo_section\[0\].impl_bram_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg\[4\]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: \[DRC REQP-1839\] RAMB36 async control check: The RAMB36E1 e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_output_out\[0\].axis_data_to_chdr_out_out/no_gen_axis_width_conv.gen_async_pyld_fifo.pyld_fifo/fifo_section\[0\].impl_bram_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop\[0\].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram has an input control pin e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_output_out\[0\].axis_data_to_chdr_out_out/no_gen_axis_width_conv.gen_async_pyld_fifo.pyld_fifo/fifo_section\[0\].impl_bram_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop\[0\].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram/ADDRARDADDR\[11\] (net: e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_output_out\[0\].axis_data_to_chdr_out_out/no_gen_axis_width_conv.gen_async_pyld_fifo.pyld_fifo/fifo_section\[0\].impl_bram_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop\[0\].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_0\[5\]) which is driven by a register (e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_output_out\[0\].axis_data_to_chdr_out_out/no_gen_axis_width_conv.gen_async_pyld_fifo.pyld_fifo/fifo_section\[0\].impl_bram_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg\[5\]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: \[DRC REQP-1839\] RAMB36 async control check: The RAMB36E1 e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_output_out\[0\].axis_data_to_chdr_out_out/no_gen_axis_width_conv.gen_async_pyld_fifo.pyld_fifo/fifo_section\[0\].impl_bram_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop\[0\].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram has an input control pin e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_output_out\[0\].axis_data_to_chdr_out_out/no_gen_axis_width_conv.gen_async_pyld_fifo.pyld_fifo/fifo_section\[0\].impl_bram_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop\[0\].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram/ADDRARDADDR\[12\] (net: e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_output_out\[0\].axis_data_to_chdr_out_out/no_gen_axis_width_conv.gen_async_pyld_fifo.pyld_fifo/fifo_section\[0\].impl_bram_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop\[0\].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_0\[6\]) which is driven by a register (e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_output_out\[0\].axis_data_to_chdr_out_out/no_gen_axis_width_conv.gen_async_pyld_fifo.pyld_fifo/fifo_section\[0\].impl_bram_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg\[6\]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: \[DRC REQP-1839\] RAMB36 async control check: The RAMB36E1 e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_output_out\[0\].axis_data_to_chdr_out_out/no_gen_axis_width_conv.gen_async_pyld_fifo.pyld_fifo/fifo_section\[0\].impl_bram_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop\[0\].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram has an input control pin e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_output_out\[0\].axis_data_to_chdr_out_out/no_gen_axis_width_conv.gen_async_pyld_fifo.pyld_fifo/fifo_section\[0\].impl_bram_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop\[0\].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram/ADDRARDADDR\[13\] (net: e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_output_out\[0\].axis_data_to_chdr_out_out/no_gen_axis_width_conv.gen_async_pyld_fifo.pyld_fifo/fifo_section\[0\].impl_bram_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop\[0\].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_0\[7\]) which is driven by a register (e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_output_out\[0\].axis_data_to_chdr_out_out/no_gen_axis_width_conv.gen_async_pyld_fifo.pyld_fifo/fifo_section\[0\].impl_bram_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg\[7\]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: \[DRC REQP-1839\] RAMB36 async control check: The RAMB36E1 e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_output_out\[0\].axis_data_to_chdr_out_out/no_gen_axis_width_conv.gen_async_pyld_fifo.pyld_fifo/fifo_section\[0\].impl_bram_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop\[0\].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram has an input control pin e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_output_out\[0\].axis_data_to_chdr_out_out/no_gen_axis_width_conv.gen_async_pyld_fifo.pyld_fifo/fifo_section\[0\].impl_bram_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop\[0\].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram/ADDRARDADDR\[14\] (net: e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_output_out\[0\].axis_data_to_chdr_out_out/no_gen_axis_width_conv.gen_async_pyld_fifo.pyld_fifo/fifo_section\[0\].impl_bram_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop\[0\].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_0\[8\]) which is driven by a register (e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_output_out\[0\].axis_data_to_chdr_out_out/no_gen_axis_width_conv.gen_async_pyld_fifo.pyld_fifo/fifo_section\[0\].impl_bram_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg\[8\]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: \[DRC REQP-1839\] RAMB36 async control check: The RAMB36E1 e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_output_out\[0\].axis_data_to_chdr_out_out/no_gen_axis_width_conv.gen_async_pyld_fifo.pyld_fifo/fifo_section\[0\].impl_bram_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop\[0\].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram has an input control pin e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_output_out\[0\].axis_data_to_chdr_out_out/no_gen_axis_width_conv.gen_async_pyld_fifo.pyld_fifo/fifo_section\[0\].impl_bram_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop\[0\].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram/ADDRARDADDR\[9\] (net: e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_output_out\[0\].axis_data_to_chdr_out_out/no_gen_axis_width_conv.gen_async_pyld_fifo.pyld_fifo/fifo_section\[0\].impl_bram_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop\[0\].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_0\[3\]) which is driven by a register (e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_output_out\[0\].axis_data_to_chdr_out_out/no_gen_axis_width_conv.gen_async_pyld_fifo.pyld_fifo/fifo_section\[0\].impl_bram_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg\[3\]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: \[DRC REQP-1840\] RAMB18 async control check: The RAMB18E1 e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/ctrlport_endpoint_i/gen_ctrl_slave.slv_fifo_i/fifo_bram/ram/impl/ram_reg has an input control pin e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/ctrlport_endpoint_i/gen_ctrl_slave.slv_fifo_i/fifo_bram/ram/impl/ram_reg/ENBWREN (net: e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/ctrlport_endpoint_i/gen_ctrl_slave.slv_fifo_i/fifo_bram/ram/impl/p_0_in7_out) which is driven by a register (e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/ctrlport_endpoint_i/gen_async_fifos.in_fifo_i/fifo_section\[0\].impl_srl_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: \[DRC REQP-1840\] RAMB18 async control check: The RAMB18E1 e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/ctrlport_endpoint_i/gen_ctrl_slave.slv_fifo_i/fifo_bram/ram/impl/ram_reg has an input control pin e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/ctrlport_endpoint_i/gen_ctrl_slave.slv_fifo_i/fifo_bram/ram/impl/ram_reg/WEBWE\[0\] (net: e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/ctrlport_endpoint_i/gen_ctrl_slave.slv_fifo_i/fifo_bram/ram/impl/p_0_in7_out) which is driven by a register (e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/ctrlport_endpoint_i/gen_async_fifos.in_fifo_i/fifo_section\[0\].impl_srl_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: \[DRC REQP-1840\] RAMB18 async control check: The RAMB18E1 e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/ctrlport_endpoint_i/gen_ctrl_slave.slv_fifo_i/fifo_bram/ram/impl/ram_reg has an input control pin e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/ctrlport_endpoint_i/gen_ctrl_slave.slv_fifo_i/fifo_bram/ram/impl/ram_reg/WEBWE\[1\] (net: e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/ctrlport_endpoint_i/gen_ctrl_slave.slv_fifo_i/fifo_bram/ram/impl/p_0_in7_out) which is driven by a register (e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/ctrlport_endpoint_i/gen_async_fifos.in_fifo_i/fifo_section\[0\].impl_srl_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: \[DRC REQP-1840\] RAMB18 async control check: The RAMB18E1 e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/ctrlport_endpoint_i/gen_ctrl_slave.slv_fifo_i/fifo_bram/ram/impl/ram_reg has an input control pin e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/ctrlport_endpoint_i/gen_ctrl_slave.slv_fifo_i/fifo_bram/ram/impl/ram_reg/WEBWE\[2\] (net: e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/ctrlport_endpoint_i/gen_ctrl_slave.slv_fifo_i/fifo_bram/ram/impl/p_0_in7_out) which is driven by a register (e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/ctrlport_endpoint_i/gen_async_fifos.in_fifo_i/fifo_section\[0\].impl_srl_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: \[DRC REQP-1840\] RAMB18 async control check: The RAMB18E1 e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/ctrlport_endpoint_i/gen_ctrl_slave.slv_fifo_i/fifo_bram/ram/impl/ram_reg has an input control pin e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/ctrlport_endpoint_i/gen_ctrl_slave.slv_fifo_i/fifo_bram/ram/impl/ram_reg/WEBWE\[3\] (net: e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/ctrlport_endpoint_i/gen_ctrl_slave.slv_fifo_i/fifo_bram/ram/impl/p_0_in7_out) which is driven by a register (e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/ctrlport_endpoint_i/gen_async_fifos.in_fifo_i/fifo_section\[0\].impl_srl_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. \[00:10:42\] Starting Placer Task \[00:10:42\] Current task: Placer +++ Current Phase: Starting \[00:10:42\] Current task: Placer +++ Current Phase: 1 Placer Initialization \[00:10:42\] Current task: Placer +++ Current Phase: 1.1 Placer Initialization Netlist Sorting WARNING: \[Place 30-87\] Partially locked IO Bus is found. Following components of the IO Bus DB_EXP_1_8V are not locked: 'DB_EXP_1_8V\[30\]' 'DB_EXP_1_8V\[29\]' 'DB_EXP_1_8V\[28\]' 'DB_EXP_1_8V\[27\]' 'DB_EXP_1_8V\[26\]' 'DB_EXP_1_8V\[25\]' 'DB_EXP_1_8V\[23\]' 'DB_EXP_1_8V\[22\]' 'DB_EXP_1_8V\[21\]' 'DB_EXP_1_8V\[20\]' 'DB_EXP_1_8V\[19\]' 'DB_EXP_1_8V\[18\]' 'DB_EXP_1_8V\[17\]' 'DB_EXP_1_8V\[16\]' 'DB_EXP_1_8V\[15\]' 'DB_EXP_1_8V\[14\]' 'DB_EXP_1_8V\[13\]' 'DB_EXP_1_8V\[12\]' 'DB_EXP_1_8V\[7\]' 'DB_EXP_1_8V\[4\]' 'DB_EXP_1_8V\[3\]' 'DB_EXP_1_8V\[2\]' 'DB_EXP_1_8V\[1\]' 'DB_EXP_1_8V\[0\]' CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[0\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[10\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[11\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[12\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[13\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[14\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[15\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[16\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[17\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[18\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[19\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[1\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[20\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[21\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[22\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[23\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[24\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[25\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[26\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[27\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[28\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[29\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[2\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[30\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[31\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[3\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[4\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[5\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[6\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[7\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[8\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[9\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[0\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[16\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[17\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[18\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[19\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[1\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[20\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[21\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[22\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[23\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[24\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[25\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[26\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[27\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[28\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[29\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[2\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[30\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[31\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[0\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[10\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[11\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[12\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[13\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[14\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[15\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[16\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[17\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[18\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[19\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[1\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[20\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[21\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[22\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[23\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[24\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[25\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[26\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[27\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[28\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[29\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[2\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[30\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[31\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[3\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[4\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[5\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[6\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[7\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[8\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[9\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_out_iob_reg\[0\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_out_iob_reg\[16\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_out_iob_reg\[17\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_out_iob_reg\[18\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_out_iob_reg\[19\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_out_iob_reg\[1\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_out_iob_reg\[20\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_out_iob_reg\[21\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_out_iob_reg\[22\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_out_iob_reg\[23\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_out_iob_reg\[24\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_out_iob_reg\[25\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_out_iob_reg\[26\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_out_iob_reg\[27\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_out_iob_reg\[28\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_out_iob_reg\[29\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_out_iob_reg\[2\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. WARNING: \[Place 30-568\] A LUT 'e31x_core_inst/tpps_i_2' is driving clock pin of 25 registers. This could lead to large hold time violations. First few involved registers are: WARNING: \[Place 30-172\] Sub-optimal placement for a clock-capable IO pin and PLL pair. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. \[00:10:50\] Current task: Placer +++ Current Phase: 1.2 IO Placement/ Clock Placement/ Build Placer Device WARNING: \[Place 30-770\] High register utilization is forcing place_design to place up to 8 registers per slice which may impact placement success and/or routing congestion. \[00:11:12\] Current task: Placer +++ Current Phase: 1.3 Build Placer Netlist Model \[00:11:13\] Current task: Placer +++ Current Phase: 1.4 Constrain Clocks/Macros \[00:11:13\] Current task: Placer +++ Current Phase: 2 Global Placement \[00:11:19\] Current task: Placer +++ Current Phase: 2.1 Floorplanning \[00:11:26\] Current task: Placer +++ Current Phase: 2.2 Update Timing before SLR Path Opt \[00:12:22\] Current task: Placer +++ Current Phase: 2.4 Global Placement Core \[00:12:47\] Current task: Placer +++ Current Phase: 2.4.1 Physical Synthesis In Placer \[00:12:47\] Current task: Placer +++ Current Phase: 3 Detail Placement \[00:13:03\] Current task: Placer +++ Current Phase: 3.1 Commit Multi Column Macros \[00:13:04\] Current task: Placer +++ Current Phase: 3.3 Area Swap Optimization \[00:13:05\] Current task: Placer +++ Current Phase: 3.4 Pipeline Register Optimization \[00:13:13\] Current task: Placer +++ Current Phase: 3.5 Fast Optimization ERROR: \[Place 30-487\] The packing of instances into the device could not be obeyed. There are a total of 13300 slices in the device, of which 9737 slices are available, however, the unplaced instances require 10808 slices. Please analyze your design to determine if the number of LUTs, FFs, and/or control sets can be reduced. ERROR: \[Place 30-99\] Placer failed with error: 'Detail Placement failed please check previous errors for details.' ERROR: \[Common 17-69\] Command failed: Placer could not place all instances \[00:13:44\] Current task: Placer +++ Current Phase: 3.6 Small Shape Detail Placement \[00:13:45\] Current task: Placer +++ Current Phase: Finished \[00:13:45\] Process terminated. Status: Failure ======================================================== Warnings: 877 Critical Warnings: 122 Errors: 3 make\[1\]: \*\*\* \[Makefile.e31x.inc:121: bin\] Error 1 make\[1\]: Leaving directory '/home/grcusrp/uhd/fpga/usrp3/top/e31x' make: \*\*\* \[Makefile:80: E310_SG3\] Error 2 grcusrp@grcusrp-ThinkPad-T470:\~/uhd/fpga/usrp3/top/e31x$ grcusrp@grcusrp-ThinkPad-T470:\~/uhd/fpga/usrp3/top/e31x$ ls axi_pmu.v build-E310_SG3_IP dts e310_rfnoc_image_core.vh e31x_core.v e31x_idle.v e31x.v Makefile.e31x.inc sim build build_e31x.tcl e310_io.v e310_rfnoc_image_core.yml e31x_dram.v e31x_pins.xdc ip ppsloop.v spi_slave.v build-E310_SG3 build-ip e310_rfnoc_image_core.v e310_static_router.hex e31x_idle_pins.xdc e31x_timing.xdc Makefile setupenv.sh grcusrp@grcusrp-ThinkPad-T470:\~/uhd/fpga/usrp3/top/e31x$ ERROR: \[Place 30-487\] The packing of instances into the device could not be obeyed. There are a total of 13300 slices in the device, of which 9737 slices are available, however, the unplaced instances require 10808 slices. Please analyze your design to determine if the number of LUTs, FFs, and/or control sets can be reduced. ERROR:: command not found grcusrp@grcusrp-ThinkPad-T470:\~/uhd/fpga/usrp3/top/e31x$ ERROR: \[Place 30-99\] Placer failed with error: 'Detail Placement failed please check previous errors for details.' ERROR:: command not found grcusrp@grcusrp-ThinkPad-T470:\~/uhd/fpga/usrp3/top/e31x$ ERROR: \[Common 17-69\] Command failed: Placer could not place all instances ERROR:: command not found grcusrp@grcusrp-ThinkPad-T470:\~/uhd/fpga/usrp3/top/e31x$ \[00:13:44\] Current task: Placer +++ Current Phase: 3.6 Small Shape Detail Placement \[00:13:44\]: command not found grcusrp@grcusrp-ThinkPad-T470:\~/uhd/fpga/usrp3/top/e31x$ \[00:13:45\] Current task: Placer +++ Current Phase: Finished \[00:13:45\]: command not found grcusrp@grcusrp-ThinkPad-T470:\~/uhd/fpga/usrp3/top/e31x$ \[00:13:45\] Process terminated. Status: Failure \[00:13:45\]: command not found grcusrp@grcusrp-ThinkPad-T470:\~/uhd/fpga/usrp3/top/e31x$ cd $home grcusrp@grcusrp-ThinkPad-T470:\~$ cd /Downloads bash: cd: /Downloads: No such file or directory grcusrp@grcusrp-ThinkPad-T470:\~$ cd \\Downloads grcusrp@grcusrp-ThinkPad-T470:\~/Downloads$ ls 121-1-322-1-10-20220925.pdf Cloudpath-x64.tar.bz2 e3xx_e310_sg3_sdimg_default-v4.4.0.0.zip LSFR8.py LSFR_copy-trnasmitter-pulse.grc Xilinx.bin AR76780_Vivado_2021_1_preliminary_rev1 'e310_rfnoc_image_core(1).yml' hackRFtransmit.py 'LSFR_copy_receiver(1).grc' LSFR.py AR76780_Vivado_2021_1_preliminary_rev1.zip e310_rfnoc_image_core.yml lesson08alt_hackRFtransmit.grc LSFR_copy_receiver.grc pulse.py Cloudpath-x64 e3xx_e310_sg3_sdimg_default-v4.4.0.0 LSFR1.py LSFR_copy-trnasmitter.grc usrp_e310_fs.sdimg grcusrp@grcusrp-ThinkPad-T470:\~/Downloads$ rfnoc_image_builder -y ./e310_rfnoc_image_core.yml \[ERR\] FPGA path not found. Specify with --fpga-dir argument. grcusrp@grcusrp-ThinkPad-T470:\~/Downloads$ cd grcusrp@grcusrp-ThinkPad-T470:\~$ cd uhd grcusrp@grcusrp-ThinkPad-T470:\~/uhd$ cd fpga grcusrp@grcusrp-ThinkPad-T470:\~/uhd/fpga$ cd usrp3 grcusrp@grcusrp-ThinkPad-T470:\~/uhd/fpga/usrp3$ cd top grcusrp@grcusrp-ThinkPad-T470:\~/uhd/fpga/usrp3/top$ cd e31x grcusrp@grcusrp-ThinkPad-T470:\~/uhd/fpga/usrp3/top/e31x$ rfnoc_image_builder -y ./e310_rfnoc_image_core.yml \[INF\] Using FPGA directory /home/grcusrp/uhd/fpga \[INF\] Selected device e310 \[INF\] Using io_signatures.yml from /usr/local/share/uhd/rfnoc/core. \[INF\] Using e310_bsp.yml from /usr/local/share/uhd/rfnoc/core. \[INF\] Adding block description from duc.yml (/usr/local/share/uhd/rfnoc/blocks). \[INF\] Adding block description from split_stream.yml (/usr/local/share/uhd/rfnoc/blocks). \[INF\] Adding block description from window.yml (/usr/local/share/uhd/rfnoc/blocks). \[INF\] Adding block description from vector_iir.yml (/usr/local/share/uhd/rfnoc/blocks). \[INF\] Adding block description from addsub.yml (/usr/local/share/uhd/rfnoc/blocks). \[INF\] Adding block description from logpwr.yml (/usr/local/share/uhd/rfnoc/blocks). \[INF\] Adding block description from null_src_sink.yml (/usr/local/share/uhd/rfnoc/blocks). \[INF\] Adding block description from fir_filter.yml (/usr/local/share/uhd/rfnoc/blocks). \[INF\] Adding block description from ddc.yml (/usr/local/share/uhd/rfnoc/blocks). \[INF\] Adding block description from moving_avg.yml (/usr/local/share/uhd/rfnoc/blocks). \[INF\] Adding block description from fft_1x64.yml (/usr/local/share/uhd/rfnoc/blocks). \[INF\] Adding block description from keep_one_in_n.yml (/usr/local/share/uhd/rfnoc/blocks). \[INF\] Adding block description from radio.yml (/usr/local/share/uhd/rfnoc/blocks). \[INF\] Adding block description from switchboard.yml (/usr/local/share/uhd/rfnoc/blocks). \[INF\] Adding block description from replay.yml (/usr/local/share/uhd/rfnoc/blocks). \[INF\] Adding block description from siggen.yml (/usr/local/share/uhd/rfnoc/blocks). \[INF\] Adding block description from axi_ram_fifo.yml (/usr/local/share/uhd/rfnoc/blocks). \[INF\] Adding block description from fosphor.yml (/usr/local/share/uhd/rfnoc/blocks). \[INF\] Plausibility checks on the current configuration \[INF\] Writing static routing table to /home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_static_router.hex \[INF\] Writing image core to /home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v \[INF\] Writing image core header to /home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.vh \[INF\] Launching build with the following settings: \[INF\] \* Build Directory: /home/grcusrp/uhd/fpga/usrp3/top/e31x \[INF\] \* Target: DRAM=1 E310_SG3 \[INF\] \* Image Core File: /home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v \[INF\] \* Edge Table File: /home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_static_router.hex Setting up a 64-bit FPGA build environment for the USRP-E31x... \- Vivado: Found (/tools/Xilinx/Vivado/2021.1/bin) Installed version is Vivado v2021.1_AR76780 (64-bit) Environment successfully initialized. make -f Makefile.e31x.inc viv_ip NAME=E310_SG3_IP ARCH=zynq PART_ID=xc7z020/clg484/-3 E310_SG3=1 TOP_MODULE=e31x EXTRA_DEFS="E310_SG3=1" DEFAULT_RFNOC_IMAGE_CORE_FILE=e310_rfnoc_image_core.v DEFAULT_EDGE_FILE=/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_static_router.hex make\[1\]: Entering directory '/home/grcusrp/uhd/fpga/usrp3/top/e31x' BUILDER: Checking tools... \* GNU bash, version 5.0.17(1)-release (x86_64-pc-linux-gnu) \* Python 3.8.10 \* Vivado v2021.1_AR76780 (64-bit) IP build for E310_SG3_IP DONE . . . make\[1\]: Leaving directory '/home/grcusrp/uhd/fpga/usrp3/top/e31x' make -f Makefile.e31x.inc bin NAME=E310_SG3 ARCH=zynq PART_ID=xc7z020/clg484/-3 E310_SG3=1 ENABLE_DRAM=1 TOP_MODULE=e31x EXTRA_DEFS=" E310_SG3=1 ENABLE_DRAM=1" DEFAULT_RFNOC_IMAGE_CORE_FILE=e310_rfnoc_image_core.v DEFAULT_EDGE_FILE=/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_static_router.hex make\[1\]: Entering directory '/home/grcusrp/uhd/fpga/usrp3/top/e31x' BUILDER: Checking tools... \* GNU bash, version 5.0.17(1)-release (x86_64-pc-linux-gnu) \* Python 3.8.10 \* Vivado v2021.1_AR76780 (64-bit) Could not read parser configuration from: /home/grcusrp/uhd/fpga/usrp3/top/e31x/dev_config.json \[00:00:00\] Executing command: vivado -mode batch -source /home/grcusrp/uhd/fpga/usrp3/top/e31x/build_e31x.tcl -log build.log -journal e31x.jou WARNING: \[filemgmt 56-12\] File '/home/grcusrp/uhd/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_replay/rfnoc_block_replay_regs.vh' cannot be added to the project because it already exists in the project, skipping this file WARNING: \[filemgmt 56-12\] File '/home/grcusrp/uhd/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_replay/axis_replay.v' cannot be added to the project because it already exists in the project, skipping this file WARNING: \[filemgmt 56-12\] File '/home/grcusrp/uhd/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_replay/noc_shell_replay.v' cannot be added to the project because it already exists in the project, skipping this file WARNING: \[filemgmt 56-12\] File '/home/grcusrp/uhd/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_replay/rfnoc_block_replay.v' cannot be added to the project because it already exists in the project, skipping this file \[00:00:15\] Current task: Initialization +++ Current Phase: Starting \[00:00:15\] Current task: Initialization +++ Current Phase: Finished \[00:00:15\] Executing Tcl: synth_design -top e31x -part xc7z020clg484-3 -verilog_define E310_SG3=1 -verilog_define ENABLE_DRAM=1 -verilog_define GIT_HASH=32'hf5fac246 -verilog_define RFNOC_EDGE_TBL_FILE=/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_static_router.hex -verilog_define RFNOC_IMAGE_CORE_HDR=/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.vh -verilog_define UHD_FPGA_DIR=/home/grcusrp/uhd/fpga/usrp3/top/../.. \[00:00:15\] Starting Synthesis Command WARNING: \[Synth 8-2507\] parameter declaration becomes local in cam_priority_encoder with formal parameter declaration list \[/home/grcusrp/uhd/fpga/usrp3/lib/control/map/cam_priority_encoder.v:46\] WARNING: \[Synth 8-2507\] parameter declaration becomes local in cam_priority_encoder with formal parameter declaration list \[/home/grcusrp/uhd/fpga/usrp3/lib/control/map/cam_priority_encoder.v:47\] WARNING: \[Synth 8-2507\] parameter declaration becomes local in axis_data_swap with formal parameter declaration list \[/home/grcusrp/uhd/fpga/usrp3/lib/axi/axis_data_swap.v:54\] WARNING: \[Synth 8-2507\] parameter declaration becomes local in axis_data_swap with formal parameter declaration list \[/home/grcusrp/uhd/fpga/usrp3/lib/axi/axis_data_swap.v:55\] WARNING: \[Synth 8-2507\] parameter declaration becomes local in dds_freq_tune_duc with formal parameter declaration list \[/home/grcusrp/uhd/fpga/usrp3/lib/rfnoc/dds_freq_tune_duc.v:128\] WARNING: \[Synth 8-2507\] parameter declaration becomes local in axis_ctrl_crossbar_2d_mesh with formal parameter declaration list \[/home/grcusrp/uhd/fpga/usrp3/lib/rfnoc/crossbar/mesh_node_mapping.vh:7\] WARNING: \[Synth 8-2507\] parameter declaration becomes local in torus_2d_dor_router_single_sw with formal parameter declaration list \[/home/grcusrp/uhd/fpga/usrp3/lib/rfnoc/crossbar/mesh_node_mapping.vh:7\] WARNING: \[Synth 8-2507\] parameter declaration becomes local in mesh_2d_dor_router_single_sw with formal parameter declaration list \[/home/grcusrp/uhd/fpga/usrp3/lib/rfnoc/crossbar/mesh_node_mapping.vh:7\] WARNING: \[Synth 8-7071\] port 'CLKFBOUT' of module 'PLLE2_ADV' is unconnected for instance 'clkgen' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/ppsloop.v:44\] WARNING: \[Synth 8-7071\] port 'CLKOUT2' of module 'PLLE2_ADV' is unconnected for instance 'clkgen' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/ppsloop.v:44\] WARNING: \[Synth 8-7071\] port 'CLKOUT3' of module 'PLLE2_ADV' is unconnected for instance 'clkgen' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/ppsloop.v:44\] WARNING: \[Synth 8-7071\] port 'CLKOUT4' of module 'PLLE2_ADV' is unconnected for instance 'clkgen' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/ppsloop.v:44\] WARNING: \[Synth 8-7071\] port 'CLKOUT5' of module 'PLLE2_ADV' is unconnected for instance 'clkgen' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/ppsloop.v:44\] WARNING: \[Synth 8-7071\] port 'DO' of module 'PLLE2_ADV' is unconnected for instance 'clkgen' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/ppsloop.v:44\] WARNING: \[Synth 8-7071\] port 'DRDY' of module 'PLLE2_ADV' is unconnected for instance 'clkgen' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/ppsloop.v:44\] WARNING: \[Synth 8-7071\] port 'CLKFBIN' of module 'PLLE2_ADV' is unconnected for instance 'clkgen' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/ppsloop.v:44\] WARNING: \[Synth 8-7071\] port 'CLKIN2' of module 'PLLE2_ADV' is unconnected for instance 'clkgen' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/ppsloop.v:44\] WARNING: \[Synth 8-7071\] port 'CLKINSEL' of module 'PLLE2_ADV' is unconnected for instance 'clkgen' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/ppsloop.v:44\] WARNING: \[Synth 8-7071\] port 'DADDR' of module 'PLLE2_ADV' is unconnected for instance 'clkgen' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/ppsloop.v:44\] WARNING: \[Synth 8-7071\] port 'DCLK' of module 'PLLE2_ADV' is unconnected for instance 'clkgen' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/ppsloop.v:44\] WARNING: \[Synth 8-7071\] port 'DEN' of module 'PLLE2_ADV' is unconnected for instance 'clkgen' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/ppsloop.v:44\] WARNING: \[Synth 8-7071\] port 'DI' of module 'PLLE2_ADV' is unconnected for instance 'clkgen' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/ppsloop.v:44\] WARNING: \[Synth 8-7071\] port 'DWE' of module 'PLLE2_ADV' is unconnected for instance 'clkgen' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/ppsloop.v:44\] WARNING: \[Synth 8-7023\] instance 'clkgen' of module 'PLLE2_ADV' has 21 connections declared, but only 6 given \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/ppsloop.v:44\] WARNING: \[Synth 8-7071\] port 'reg_wr_keep' of module 'axil_regport_master' is unconnected for instance 'eth_dma_reg_mst_i' \[/home/grcusrp/uhd/fpga/usrp3/lib/rfnoc/xport/eth_internal.v:128\] WARNING: \[Synth 8-7023\] instance 'eth_dma_reg_mst_i' of module 'axil_regport_master' has 28 connections declared, but only 27 given \[/home/grcusrp/uhd/fpga/usrp3/lib/rfnoc/xport/eth_internal.v:128\] WARNING: \[Synth 8-7071\] port 'output_unencoded' of module 'cam_priority_encoder' is unconnected for instance 'priority_encoder_inst1' \[/home/grcusrp/uhd/fpga/usrp3/lib/control/map/cam_priority_encoder.v:67\] WARNING: \[Synth 8-7023\] instance 'priority_encoder_inst1' of module 'cam_priority_encoder' has 4 connections declared, but only 3 given \[/home/grcusrp/uhd/fpga/usrp3/lib/control/map/cam_priority_encoder.v:67\] WARNING: \[Synth 8-693\] zero replication count - replication ignored \[/home/grcusrp/uhd/fpga/usrp3/lib/control/map/cam_priority_encoder.v:77\] WARNING: \[Synth 8-7071\] port 'output_unencoded' of module 'cam_priority_encoder' is unconnected for instance 'priority_encoder_inst2' \[/home/grcusrp/uhd/fpga/usrp3/lib/control/map/cam_priority_encoder.v:76\] WARNING: \[Synth 8-7023\] instance 'priority_encoder_inst2' of module 'cam_priority_encoder' has 4 connections declared, but only 3 given \[/home/grcusrp/uhd/fpga/usrp3/lib/control/map/cam_priority_encoder.v:76\] WARNING: \[Synth 8-7071\] port 'output_unencoded' of module 'cam_priority_encoder' is unconnected for instance 'priority_encoder_inst1' \[/home/grcusrp/uhd/fpga/usrp3/lib/control/map/cam_priority_encoder.v:67\] WARNING: \[Synth 8-7023\] instance 'priority_encoder_inst1' of module 'cam_priority_encoder' has 4 connections declared, but only 3 given \[/home/grcusrp/uhd/fpga/usrp3/lib/control/map/cam_priority_encoder.v:67\] WARNING: \[Synth 8-693\] zero replication count - replication ignored \[/home/grcusrp/uhd/fpga/usrp3/lib/control/map/cam_priority_encoder.v:77\] WARNING: \[Synth 8-7071\] port 'output_unencoded' of module 'cam_priority_encoder' is unconnected for instance 'priority_encoder_inst2' \[/home/grcusrp/uhd/fpga/usrp3/lib/control/map/cam_priority_encoder.v:76\] WARNING: \[Synth 8-7023\] instance 'priority_encoder_inst2' of module 'cam_priority_encoder' has 4 connections declared, but only 3 given \[/home/grcusrp/uhd/fpga/usrp3/lib/control/map/cam_priority_encoder.v:76\] WARNING: \[Synth 8-7071\] port 'output_unencoded' of module 'cam_priority_encoder' is unconnected for instance 'priority_encoder_inst1' \[/home/grcusrp/uhd/fpga/usrp3/lib/control/map/cam_priority_encoder.v:67\] WARNING: \[Synth 8-7023\] instance 'priority_encoder_inst1' of module 'cam_priority_encoder' has 4 connections declared, but only 3 given \[/home/grcusrp/uhd/fpga/usrp3/lib/control/map/cam_priority_encoder.v:67\] WARNING: \[Synth 8-693\] zero replication count - replication ignored \[/home/grcusrp/uhd/fpga/usrp3/lib/control/map/cam_priority_encoder.v:77\] WARNING: \[Synth 8-7071\] port 'output_unencoded' of module 'cam_priority_encoder' is unconnected for instance 'priority_encoder_inst2' \[/home/grcusrp/uhd/fpga/usrp3/lib/control/map/cam_priority_encoder.v:76\] WARNING: \[Synth 8-7023\] instance 'priority_encoder_inst2' of module 'cam_priority_encoder' has 4 connections declared, but only 3 given \[/home/grcusrp/uhd/fpga/usrp3/lib/control/map/cam_priority_encoder.v:76\] WARNING: \[Synth 8-7071\] port 'output_unencoded' of module 'cam_priority_encoder' is unconnected for instance 'priority_encoder_inst1' \[/home/grcusrp/uhd/fpga/usrp3/lib/control/map/cam_priority_encoder.v:67\] WARNING: \[Synth 8-7023\] instance 'priority_encoder_inst1' of module 'cam_priority_encoder' has 4 connections declared, but only 3 given \[/home/grcusrp/uhd/fpga/usrp3/lib/control/map/cam_priority_encoder.v:67\] WARNING: \[Synth 8-693\] zero replication count - replication ignored \[/home/grcusrp/uhd/fpga/usrp3/lib/control/map/cam_priority_encoder.v:77\] WARNING: \[Synth 8-7071\] port 'output_unencoded' of module 'cam_priority_encoder' is unconnected for instance 'priority_encoder_inst2' \[/home/grcusrp/uhd/fpga/usrp3/lib/control/map/cam_priority_encoder.v:76\] WARNING: \[Synth 8-7023\] instance 'priority_encoder_inst2' of module 'cam_priority_encoder' has 4 connections declared, but only 3 given \[/home/grcusrp/uhd/fpga/usrp3/lib/control/map/cam_priority_encoder.v:76\] WARNING: \[Synth 8-7071\] port 'output_unencoded' of module 'cam_priority_encoder' is unconnected for instance 'priority_encoder_inst1' \[/home/grcusrp/uhd/fpga/usrp3/lib/control/map/cam_priority_encoder.v:67\] WARNING: \[Synth 8-7023\] instance 'priority_encoder_inst1' of module 'cam_priority_encoder' has 4 connections declared, but only 3 given \[/home/grcusrp/uhd/fpga/usrp3/lib/control/map/cam_priority_encoder.v:67\] WARNING: \[Synth 8-693\] zero replication count - replication ignored \[/home/grcusrp/uhd/fpga/usrp3/lib/control/map/cam_priority_encoder.v:77\] WARNING: \[Synth 8-7071\] port 'output_unencoded' of module 'cam_priority_encoder' is unconnected for instance 'priority_encoder_inst2' \[/home/grcusrp/uhd/fpga/usrp3/lib/control/map/cam_priority_encoder.v:76\] WARNING: \[Synth 8-7023\] instance 'priority_encoder_inst2' of module 'cam_priority_encoder' has 4 connections declared, but only 3 given \[/home/grcusrp/uhd/fpga/usrp3/lib/control/map/cam_priority_encoder.v:76\] WARNING: \[Synth 8-689\] width (32) of port connection 's_axi_awaddr' does not match port width (14) of module 'eth_internal' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x.v:440\] WARNING: \[Synth 8-689\] width (32) of port connection 's_axi_araddr' does not match port width (14) of module 'eth_internal' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x.v:453\] WARNING: \[Synth 8-7071\] port 'm_axi_awprot' of module 'e31x_ps_bd_auto_cc_2' is unconnected for instance 'auto_cc' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/synth/e31x_ps_bd.v:3225\] WARNING: \[Synth 8-7071\] port 'm_axi_wstrb' of module 'e31x_ps_bd_auto_cc_2' is unconnected for instance 'auto_cc' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/synth/e31x_ps_bd.v:3225\] WARNING: \[Synth 8-7071\] port 'm_axi_arprot' of module 'e31x_ps_bd_auto_cc_2' is unconnected for instance 'auto_cc' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/synth/e31x_ps_bd.v:3225\] WARNING: \[Synth 8-7023\] instance 'auto_cc' of module 'e31x_ps_bd_auto_cc_2' has 42 connections declared, but only 39 given \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/synth/e31x_ps_bd.v:3225\] WARNING: \[Synth 8-7071\] port 'aclk2x' of module 'axi_register_slice_v2_1_24_axi_register_slice' is unconnected for instance 'SI_REG' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/ipshared/6e0d/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4392\] WARNING: \[Synth 8-7023\] instance 'SI_REG' of module 'axi_register_slice_v2_1_24_axi_register_slice' has 93 connections declared, but only 92 given \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/ipshared/6e0d/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4392\] WARNING: \[Synth 8-7071\] port 'aclk2x' of module 'axi_register_slice_v2_1_24_axi_register_slice' is unconnected for instance 'MI_REG' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/ipshared/6e0d/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4647\] WARNING: \[Synth 8-7023\] instance 'MI_REG' of module 'axi_register_slice_v2_1_24_axi_register_slice' has 93 connections declared, but only 92 given \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/ipshared/6e0d/hdl/axi_protocol_converter_v2_1_vl_rfs.v:4647\] WARNING: \[Synth 8-7071\] port 'axi_dma_tstvec' of module 'e31x_ps_bd_axi_dma_eth_internal_0' is unconnected for instance 'axi_dma_eth_internal' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/synth/e31x_ps_bd.v:420\] WARNING: \[Synth 8-7023\] instance 'axi_dma_eth_internal' of module 'e31x_ps_bd_axi_dma_eth_internal_0' has 94 connections declared, but only 93 given \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/synth/e31x_ps_bd.v:420\] WARNING: \[Synth 8-7071\] port 'M_AXI_GP0_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/synth/e31x_ps_bd_processing_system7_0_0.v:828\] WARNING: \[Synth 8-7071\] port 'M_AXI_GP1_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/synth/e31x_ps_bd_processing_system7_0_0.v:828\] WARNING: \[Synth 8-7071\] port 'S_AXI_GP0_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/synth/e31x_ps_bd_processing_system7_0_0.v:828\] WARNING: \[Synth 8-7071\] port 'S_AXI_GP1_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/synth/e31x_ps_bd_processing_system7_0_0.v:828\] WARNING: \[Synth 8-7071\] port 'S_AXI_ACP_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/synth/e31x_ps_bd_processing_system7_0_0.v:828\] WARNING: \[Synth 8-7071\] port 'S_AXI_HP0_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/synth/e31x_ps_bd_processing_system7_0_0.v:828\] WARNING: \[Synth 8-7071\] port 'S_AXI_HP1_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/synth/e31x_ps_bd_processing_system7_0_0.v:828\] WARNING: \[Synth 8-7071\] port 'S_AXI_HP2_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/synth/e31x_ps_bd_processing_system7_0_0.v:828\] WARNING: \[Synth 8-7071\] port 'S_AXI_HP3_ARESETN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/synth/e31x_ps_bd_processing_system7_0_0.v:828\] WARNING: \[Synth 8-7071\] port 'DMA0_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/synth/e31x_ps_bd_processing_system7_0_0.v:828\] WARNING: \[Synth 8-7071\] port 'DMA1_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/synth/e31x_ps_bd_processing_system7_0_0.v:828\] WARNING: \[Synth 8-7071\] port 'DMA2_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/synth/e31x_ps_bd_processing_system7_0_0.v:828\] WARNING: \[Synth 8-7071\] port 'DMA3_RSTN' of module 'processing_system7_v5_5_processing_system7' is unconnected for instance 'inst' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/synth/e31x_ps_bd_processing_system7_0_0.v:828\] WARNING: \[Synth 8-7023\] instance 'inst' of module 'processing_system7_v5_5_processing_system7' has 685 connections declared, but only 672 given \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/synth/e31x_ps_bd_processing_system7_0_0.v:828\] WARNING: \[Synth 8-7071\] port 'S_AXI_GP0_BID' of module 'e31x_ps_bd_processing_system7_0_0' is unconnected for instance 'processing_system7_0' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/synth/e31x_ps_bd.v:1478\] WARNING: \[Synth 8-7071\] port 'S_AXI_GP0_RID' of module 'e31x_ps_bd_processing_system7_0_0' is unconnected for instance 'processing_system7_0' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/synth/e31x_ps_bd.v:1478\] WARNING: \[Synth 8-7071\] port 'S_AXI_HP1_ARREADY' of module 'e31x_ps_bd_processing_system7_0_0' is unconnected for instance 'processing_system7_0' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/synth/e31x_ps_bd.v:1478\] WARNING: \[Synth 8-7071\] port 'S_AXI_HP1_RLAST' of module 'e31x_ps_bd_processing_system7_0_0' is unconnected for instance 'processing_system7_0' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/synth/e31x_ps_bd.v:1478\] WARNING: \[Synth 8-7071\] port 'S_AXI_HP1_RVALID' of module 'e31x_ps_bd_processing_system7_0_0' is unconnected for instance 'processing_system7_0' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/synth/e31x_ps_bd.v:1478\] WARNING: \[Synth 8-7071\] port 'S_AXI_HP1_RRESP' of module 'e31x_ps_bd_processing_system7_0_0' is unconnected for instance 'processing_system7_0' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/synth/e31x_ps_bd.v:1478\] WARNING: \[Synth 8-7071\] port 'S_AXI_HP1_BID' of module 'e31x_ps_bd_processing_system7_0_0' is unconnected for instance 'processing_system7_0' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/synth/e31x_ps_bd.v:1478\] WARNING: \[Synth 8-7071\] port 'S_AXI_HP1_RID' of module 'e31x_ps_bd_processing_system7_0_0' is unconnected for instance 'processing_system7_0' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/synth/e31x_ps_bd.v:1478\] WARNING: \[Synth 8-7071\] port 'S_AXI_HP1_RDATA' of module 'e31x_ps_bd_processing_system7_0_0' is unconnected for instance 'processing_system7_0' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/synth/e31x_ps_bd.v:1478\] WARNING: \[Synth 8-7071\] port 'S_AXI_HP1_RCOUNT' of module 'e31x_ps_bd_processing_system7_0_0' is unconnected for instance 'processing_system7_0' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/synth/e31x_ps_bd.v:1478\] WARNING: \[Synth 8-7071\] port 'S_AXI_HP1_WCOUNT' of module 'e31x_ps_bd_processing_system7_0_0' is unconnected for instance 'processing_system7_0' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/synth/e31x_ps_bd.v:1478\] WARNING: \[Synth 8-7071\] port 'S_AXI_HP1_RACOUNT' of module 'e31x_ps_bd_processing_system7_0_0' is unconnected for instance 'processing_system7_0' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/synth/e31x_ps_bd.v:1478\] WARNING: \[Synth 8-7071\] port 'S_AXI_HP1_WACOUNT' of module 'e31x_ps_bd_processing_system7_0_0' is unconnected for instance 'processing_system7_0' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/synth/e31x_ps_bd.v:1478\] WARNING: \[Synth 8-7071\] port 'S_AXI_HP2_AWREADY' of module 'e31x_ps_bd_processing_system7_0_0' is unconnected for instance 'processing_system7_0' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/synth/e31x_ps_bd.v:1478\] WARNING: \[Synth 8-7071\] port 'S_AXI_HP2_BVALID' of module 'e31x_ps_bd_processing_system7_0_0' is unconnected for instance 'processing_system7_0' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/synth/e31x_ps_bd.v:1478\] WARNING: \[Synth 8-7071\] port 'S_AXI_HP2_WREADY' of module 'e31x_ps_bd_processing_system7_0_0' is unconnected for instance 'processing_system7_0' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/synth/e31x_ps_bd.v:1478\] WARNING: \[Synth 8-7071\] port 'S_AXI_HP2_BRESP' of module 'e31x_ps_bd_processing_system7_0_0' is unconnected for instance 'processing_system7_0' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/synth/e31x_ps_bd.v:1478\] WARNING: \[Synth 8-7071\] port 'S_AXI_HP2_BID' of module 'e31x_ps_bd_processing_system7_0_0' is unconnected for instance 'processing_system7_0' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/synth/e31x_ps_bd.v:1478\] WARNING: \[Synth 8-7071\] port 'S_AXI_HP2_RID' of module 'e31x_ps_bd_processing_system7_0_0' is unconnected for instance 'processing_system7_0' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/synth/e31x_ps_bd.v:1478\] WARNING: \[Synth 8-7071\] port 'S_AXI_HP2_RCOUNT' of module 'e31x_ps_bd_processing_system7_0_0' is unconnected for instance 'processing_system7_0' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/synth/e31x_ps_bd.v:1478\] WARNING: \[Synth 8-7071\] port 'S_AXI_HP2_WCOUNT' of module 'e31x_ps_bd_processing_system7_0_0' is unconnected for instance 'processing_system7_0' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/synth/e31x_ps_bd.v:1478\] WARNING: \[Synth 8-7071\] port 'S_AXI_HP2_RACOUNT' of module 'e31x_ps_bd_processing_system7_0_0' is unconnected for instance 'processing_system7_0' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/synth/e31x_ps_bd.v:1478\] WARNING: \[Synth 8-7071\] port 'S_AXI_HP2_WACOUNT' of module 'e31x_ps_bd_processing_system7_0_0' is unconnected for instance 'processing_system7_0' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/synth/e31x_ps_bd.v:1478\] WARNING: \[Synth 8-7023\] instance 'processing_system7_0' of module 'e31x_ps_bd_processing_system7_0_0' has 229 connections declared, but only 206 given \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/synth/e31x_ps_bd.v:1478\] WARNING: \[Synth 8-7071\] port 'mb_reset' of module 'bd_cc08_psr_aclk_0' is unconnected for instance 'psr_aclk' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_smartconnect_dma_0/bd_0/synth/bd_cc08.v:798\] WARNING: \[Synth 8-7071\] port 'bus_struct_reset' of module 'bd_cc08_psr_aclk_0' is unconnected for instance 'psr_aclk' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_smartconnect_dma_0/bd_0/synth/bd_cc08.v:798\] WARNING: \[Synth 8-7071\] port 'peripheral_reset' of module 'bd_cc08_psr_aclk_0' is unconnected for instance 'psr_aclk' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_smartconnect_dma_0/bd_0/synth/bd_cc08.v:798\] WARNING: \[Synth 8-7071\] port 'peripheral_aresetn' of module 'bd_cc08_psr_aclk_0' is unconnected for instance 'psr_aclk' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_smartconnect_dma_0/bd_0/synth/bd_cc08.v:798\] WARNING: \[Synth 8-7023\] instance 'psr_aclk' of module 'bd_cc08_psr_aclk_0' has 10 connections declared, but only 6 given \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_smartconnect_dma_0/bd_0/synth/bd_cc08.v:798\] WARNING: \[Synth 8-7071\] port 'm_axi_awburst' of module 'bd_cc08_s00tr_0' is unconnected for instance 's00_transaction_regulator' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_smartconnect_dma_0/bd_0/synth/bd_cc08.v:1706\] WARNING: \[Synth 8-7071\] port 'm_axi_arburst' of module 'bd_cc08_s00tr_0' is unconnected for instance 's00_transaction_regulator' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_smartconnect_dma_0/bd_0/synth/bd_cc08.v:1706\] WARNING: \[Synth 8-7023\] instance 's00_transaction_regulator' of module 'bd_cc08_s00tr_0' has 82 connections declared, but only 80 given \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_smartconnect_dma_0/bd_0/synth/bd_cc08.v:1706\] WARNING: \[Synth 8-6104\] Input port 'PS_CLK' has an internal driver \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x.v:541\] WARNING: \[Synth 8-6104\] Input port 'PS_PORB' has an internal driver \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x.v:542\] WARNING: \[Synth 8-6104\] Input port 'PS_SRSTB' has an internal driver \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x.v:543\] WARNING: \[Synth 8-689\] width (32) of port connection 'm_axi_eth_internal_araddr' does not match port width (31) of module 'e31x_ps_bd' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x.v:577\] WARNING: \[Synth 8-689\] width (32) of port connection 'm_axi_eth_internal_awaddr' does not match port width (31) of module 'e31x_ps_bd' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x.v:581\] WARNING: \[Synth 8-689\] width (1) of port connection 'm_axi_xbar_arprot' does not match port width (3) of module 'e31x_ps_bd' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x.v:611\] WARNING: \[Synth 8-689\] width (1) of port connection 'm_axi_xbar_awprot' does not match port width (3) of module 'e31x_ps_bd' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x.v:615\] WARNING: \[Synth 8-7071\] port 'CE' of module 'BUFR' is unconnected for instance 'bufr_rx_clk' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_io.v:44\] WARNING: \[Synth 8-7071\] port 'CLR' of module 'BUFR' is unconnected for instance 'bufr_rx_clk' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_io.v:44\] WARNING: \[Synth 8-7023\] instance 'bufr_rx_clk' of module 'BUFR' has 4 connections declared, but only 2 given \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_io.v:44\] WARNING: \[Synth 8-7071\] port 'deepsleep' of module 'blk_mem_gen_v8_4_4' is unconnected for instance 'w_buffer' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/ipshared/3d13/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:10152\] WARNING: \[Synth 8-7071\] port 'shutdown' of module 'blk_mem_gen_v8_4_4' is unconnected for instance 'w_buffer' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/ipshared/3d13/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:10152\] WARNING: \[Synth 8-7071\] port 'rsta_busy' of module 'blk_mem_gen_v8_4_4' is unconnected for instance 'w_buffer' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/ipshared/3d13/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:10152\] WARNING: \[Synth 8-7071\] port 'rstb_busy' of module 'blk_mem_gen_v8_4_4' is unconnected for instance 'w_buffer' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/ipshared/3d13/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:10152\] WARNING: \[Synth 8-7023\] instance 'w_buffer' of module 'blk_mem_gen_v8_4_4' has 63 connections declared, but only 59 given \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/ipshared/3d13/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:10152\] WARNING: \[Synth 8-7071\] port 'aclk2x' of module 'axi_register_slice_v2_1_24_axi_register_slice' is unconnected for instance 's_aw_reg' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/ipshared/3d13/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:10660\] WARNING: \[Synth 8-7023\] instance 's_aw_reg' of module 'axi_register_slice_v2_1_24_axi_register_slice' has 93 connections declared, but only 92 given \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/ipshared/3d13/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:10660\] WARNING: \[Synth 8-7071\] port 'aclk2x' of module 'axi_register_slice_v2_1_24_axi_register_slice' is unconnected for instance 'si_register_slice_inst' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/ipshared/3d13/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:7379\] WARNING: \[Synth 8-7023\] instance 'si_register_slice_inst' of module 'axi_register_slice_v2_1_24_axi_register_slice' has 93 connections declared, but only 92 given \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/ipshared/3d13/hdl/axi_dwidth_converter_v2_1_vlsyn_rfs.v:7379\] WARNING: \[Synth 8-7071\] port 'm_axi_awregion' of module 'axi_inter_2x64_128_bd_s00_width_conv_0' is unconnected for instance 's00_width_conv' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/synth/axi_inter_2x64_128_bd.v:574\] WARNING: \[Synth 8-7071\] port 'm_axi_arregion' of module 'axi_inter_2x64_128_bd_s00_width_conv_0' is unconnected for instance 's00_width_conv' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/synth/axi_inter_2x64_128_bd.v:574\] WARNING: \[Synth 8-7023\] instance 's00_width_conv' of module 'axi_inter_2x64_128_bd_s00_width_conv_0' has 78 connections declared, but only 76 given \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/synth/axi_inter_2x64_128_bd.v:574\] WARNING: \[Synth 8-7071\] port 'm_axi_awregion' of module 'axi_inter_2x64_128_bd_s01_width_conv_0' is unconnected for instance 's01_width_conv' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/synth/axi_inter_2x64_128_bd.v:651\] WARNING: \[Synth 8-7071\] port 'm_axi_arregion' of module 'axi_inter_2x64_128_bd_s01_width_conv_0' is unconnected for instance 's01_width_conv' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/synth/axi_inter_2x64_128_bd.v:651\] WARNING: \[Synth 8-7023\] instance 's01_width_conv' of module 'axi_inter_2x64_128_bd_s01_width_conv_0' has 78 connections declared, but only 76 given \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/synth/axi_inter_2x64_128_bd.v:651\] WARNING: \[Synth 8-7071\] port 'aclk2x' of module 'axi_register_slice_v2_1_24_axi_register_slice' is unconnected for instance 'reg_slice_mi' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/ipshared/3917/hdl/axi_crossbar_v2_1_vl_rfs.v:3122\] WARNING: \[Synth 8-7023\] instance 'reg_slice_mi' of module 'axi_register_slice_v2_1_24_axi_register_slice' has 93 connections declared, but only 92 given \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/ipshared/3917/hdl/axi_crossbar_v2_1_vl_rfs.v:3122\] WARNING: \[Synth 8-7071\] port 'aclk2x' of module 'axi_register_slice_v2_1_24_axi_register_slice' is unconnected for instance 'reg_slice_mi' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/ipshared/3917/hdl/axi_crossbar_v2_1_vl_rfs.v:3122\] WARNING: \[Synth 8-7023\] instance 'reg_slice_mi' of module 'axi_register_slice_v2_1_24_axi_register_slice' has 93 connections declared, but only 92 given \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/ipshared/3917/hdl/axi_crossbar_v2_1_vl_rfs.v:3122\] WARNING: \[Synth 8-7071\] port 's_axi_bid' of module 'axi_inter_2x64_128_bd_xbar_0' is unconnected for instance 'xbar' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/synth/axi_inter_2x64_128_bd.v:728\] WARNING: \[Synth 8-7071\] port 's_axi_rid' of module 'axi_inter_2x64_128_bd_xbar_0' is unconnected for instance 'xbar' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/synth/axi_inter_2x64_128_bd.v:728\] WARNING: \[Synth 8-7023\] instance 'xbar' of module 'axi_inter_2x64_128_bd_xbar_0' has 78 connections declared, but only 76 given \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/synth/axi_inter_2x64_128_bd.v:728\] WARNING: \[Synth 8-689\] width (12) of port connection 'M00_AXI_arid' does not match port width (1) of module 'axi_inter_2x64_128_bd' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_dram.v:218\] WARNING: \[Synth 8-689\] width (12) of port connection 'M00_AXI_awid' does not match port width (1) of module 'axi_inter_2x64_128_bd' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_dram.v:230\] WARNING: \[Synth 8-689\] width (12) of port connection 'M00_AXI_bid' does not match port width (1) of module 'axi_inter_2x64_128_bd' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_dram.v:239\] WARNING: \[Synth 8-689\] width (12) of port connection 'M00_AXI_rid' does not match port width (1) of module 'axi_inter_2x64_128_bd' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_dram.v:244\] WARNING: \[Synth 8-689\] width (64) of port connection 'dram_axi_araddr' does not match port width (58) of module 'e31x_dram' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:766\] WARNING: \[Synth 8-689\] width (64) of port connection 'dram_axi_awaddr' does not match port width (58) of module 'e31x_dram' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:778\] WARNING: \[Synth 8-7071\] port 'time_increment' of module 'timekeeper' is unconnected for instance 'timekeeper_i' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:664\] WARNING: \[Synth 8-7023\] instance 'timekeeper_i' of module 'timekeeper' has 15 connections declared, but only 14 given \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:664\] WARNING: \[Synth 8-693\] zero replication count - replication ignored \[/home/grcusrp/uhd/fpga/usrp3/lib/rfnoc/core/chdr_data_swapper.v:189\] WARNING: \[Synth 8-693\] zero replication count - replication ignored \[/home/grcusrp/uhd/fpga/usrp3/lib/rfnoc/core/chdr_data_swapper.v:189\] WARNING: \[Synth 8-689\] width (256) of port connection 'radio_rx_data' does not match port width (64) of module 'rfnoc_block_radio' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:620\] WARNING: \[Synth 8-689\] width (8) of port connection 'radio_rx_stb' does not match port width (2) of module 'rfnoc_block_radio' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:621\] WARNING: \[Synth 8-689\] width (8) of port connection 'radio_rx_running' does not match port width (2) of module 'rfnoc_block_radio' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:622\] WARNING: \[Synth 8-689\] width (256) of port connection 'radio_tx_data' does not match port width (64) of module 'rfnoc_block_radio' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:623\] WARNING: \[Synth 8-689\] width (8) of port connection 'radio_tx_stb' does not match port width (2) of module 'rfnoc_block_radio' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:624\] WARNING: \[Synth 8-689\] width (8) of port connection 'radio_tx_running' does not match port width (2) of module 'rfnoc_block_radio' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:625\] WARNING: \[Synth 8-689\] width (4) of port connection 'm_axi_awid' does not match port width (2) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:719\] WARNING: \[Synth 8-689\] width (192) of port connection 'm_axi_awaddr' does not match port width (60) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:720\] WARNING: \[Synth 8-689\] width (32) of port connection 'm_axi_awlen' does not match port width (16) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:721\] WARNING: \[Synth 8-689\] width (12) of port connection 'm_axi_awsize' does not match port width (6) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:722\] WARNING: \[Synth 8-689\] width (8) of port connection 'm_axi_awburst' does not match port width (4) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:723\] WARNING: \[Synth 8-689\] width (4) of port connection 'm_axi_awlock' does not match port width (2) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:724\] WARNING: \[Synth 8-689\] width (16) of port connection 'm_axi_awcache' does not match port width (8) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:725\] WARNING: \[Synth 8-689\] width (12) of port connection 'm_axi_awprot' does not match port width (6) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:726\] WARNING: \[Synth 8-689\] width (16) of port connection 'm_axi_awqos' does not match port width (8) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:727\] WARNING: \[Synth 8-689\] width (16) of port connection 'm_axi_awregion' does not match port width (8) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:728\] WARNING: \[Synth 8-689\] width (4) of port connection 'm_axi_awuser' does not match port width (2) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:729\] WARNING: \[Synth 8-689\] width (4) of port connection 'm_axi_awvalid' does not match port width (2) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:730\] WARNING: \[Synth 8-689\] width (4) of port connection 'm_axi_awready' does not match port width (2) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:731\] WARNING: \[Synth 8-689\] width (2048) of port connection 'm_axi_wdata' does not match port width (128) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:732\] WARNING: \[Synth 8-689\] width (256) of port connection 'm_axi_wstrb' does not match port width (16) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:733\] WARNING: \[Synth 8-689\] width (4) of port connection 'm_axi_wlast' does not match port width (2) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:734\] WARNING: \[Synth 8-689\] width (4) of port connection 'm_axi_wuser' does not match port width (2) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:735\] WARNING: \[Synth 8-689\] width (4) of port connection 'm_axi_wvalid' does not match port width (2) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:736\] WARNING: \[Synth 8-689\] width (4) of port connection 'm_axi_wready' does not match port width (2) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:737\] WARNING: \[Synth 8-689\] width (4) of port connection 'm_axi_bid' does not match port width (2) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:738\] WARNING: \[Synth 8-689\] width (8) of port connection 'm_axi_bresp' does not match port width (4) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:739\] WARNING: \[Synth 8-689\] width (4) of port connection 'm_axi_buser' does not match port width (2) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:740\] WARNING: \[Synth 8-689\] width (4) of port connection 'm_axi_bvalid' does not match port width (2) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:741\] WARNING: \[Synth 8-689\] width (4) of port connection 'm_axi_bready' does not match port width (2) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:742\] WARNING: \[Synth 8-689\] width (4) of port connection 'm_axi_arid' does not match port width (2) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:743\] WARNING: \[Synth 8-689\] width (192) of port connection 'm_axi_araddr' does not match port width (60) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:744\] WARNING: \[Synth 8-689\] width (32) of port connection 'm_axi_arlen' does not match port width (16) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:745\] WARNING: \[Synth 8-689\] width (12) of port connection 'm_axi_arsize' does not match port width (6) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:746\] WARNING: \[Synth 8-689\] width (8) of port connection 'm_axi_arburst' does not match port width (4) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:747\] WARNING: \[Synth 8-689\] width (4) of port connection 'm_axi_arlock' does not match port width (2) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:748\] WARNING: \[Synth 8-689\] width (16) of port connection 'm_axi_arcache' does not match port width (8) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:749\] WARNING: \[Synth 8-689\] width (12) of port connection 'm_axi_arprot' does not match port width (6) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:750\] WARNING: \[Synth 8-689\] width (16) of port connection 'm_axi_arqos' does not match port width (8) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:751\] WARNING: \[Synth 8-689\] width (16) of port connection 'm_axi_arregion' does not match port width (8) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:752\] WARNING: \[Synth 8-689\] width (4) of port connection 'm_axi_aruser' does not match port width (2) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:753\] WARNING: \[Synth 8-689\] width (4) of port connection 'm_axi_arvalid' does not match port width (2) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:754\] WARNING: \[Synth 8-689\] width (4) of port connection 'm_axi_arready' does not match port width (2) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:755\] WARNING: \[Synth 8-689\] width (4) of port connection 'm_axi_rid' does not match port width (2) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:756\] WARNING: \[Synth 8-689\] width (2048) of port connection 'm_axi_rdata' does not match port width (128) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:757\] WARNING: \[Synth 8-689\] width (8) of port connection 'm_axi_rresp' does not match port width (4) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:758\] WARNING: \[Synth 8-689\] width (4) of port connection 'm_axi_rlast' does not match port width (2) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:759\] WARNING: \[Synth 8-689\] width (4) of port connection 'm_axi_ruser' does not match port width (2) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:760\] WARNING: \[Synth 8-689\] width (4) of port connection 'm_axi_rvalid' does not match port width (2) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:761\] WARNING: \[Synth 8-689\] width (4) of port connection 'm_axi_rready' does not match port width (2) of module 'rfnoc_block_replay' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e310_rfnoc_image_core.v:762\] WARNING: \[Synth 8-689\] width (2) of port connection 'radio_rx_running' does not match port width (8) of module 'rfnoc_image_core' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:839\] WARNING: \[Synth 8-689\] width (64) of port connection 'radio_tx_data' does not match port width (256) of module 'rfnoc_image_core' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:841\] WARNING: \[Synth 8-689\] width (2) of port connection 'radio_tx_running' does not match port width (8) of module 'rfnoc_image_core' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:842\] WARNING: \[Synth 8-689\] width (2) of port connection 'm_axi_awid' does not match port width (4) of module 'rfnoc_image_core' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:844\] WARNING: \[Synth 8-689\] width (64) of port connection 'm_axi_awaddr' does not match port width (192) of module 'rfnoc_image_core' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:845\] WARNING: \[Synth 8-689\] width (16) of port connection 'm_axi_awlen' does not match port width (32) of module 'rfnoc_image_core' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:846\] WARNING: \[Synth 8-689\] width (6) of port connection 'm_axi_awsize' does not match port width (12) of module 'rfnoc_image_core' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:847\] WARNING: \[Synth 8-689\] width (4) of port connection 'm_axi_awburst' does not match port width (8) of module 'rfnoc_image_core' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:848\] WARNING: \[Synth 8-689\] width (2) of port connection 'm_axi_awlock' does not match port width (4) of module 'rfnoc_image_core' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:849\] WARNING: \[Synth 8-689\] width (8) of port connection 'm_axi_awcache' does not match port width (16) of module 'rfnoc_image_core' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:850\] WARNING: \[Synth 8-689\] width (6) of port connection 'm_axi_awprot' does not match port width (12) of module 'rfnoc_image_core' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:851\] WARNING: \[Synth 8-689\] width (8) of port connection 'm_axi_awqos' does not match port width (16) of module 'rfnoc_image_core' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:852\] WARNING: \[Synth 8-689\] width (8) of port connection 'm_axi_awregion' does not match port width (16) of module 'rfnoc_image_core' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:853\] WARNING: \[Synth 8-689\] width (2) of port connection 'm_axi_awvalid' does not match port width (4) of module 'rfnoc_image_core' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:855\] WARNING: \[Synth 8-689\] width (128) of port connection 'm_axi_wdata' does not match port width (2048) of module 'rfnoc_image_core' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:857\] WARNING: \[Synth 8-689\] width (16) of port connection 'm_axi_wstrb' does not match port width (256) of module 'rfnoc_image_core' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:858\] WARNING: \[Synth 8-689\] width (2) of port connection 'm_axi_wlast' does not match port width (4) of module 'rfnoc_image_core' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:859\] WARNING: \[Synth 8-689\] width (2) of port connection 'm_axi_wvalid' does not match port width (4) of module 'rfnoc_image_core' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:861\] WARNING: \[Synth 8-689\] width (2) of port connection 'm_axi_bready' does not match port width (4) of module 'rfnoc_image_core' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:867\] WARNING: \[Synth 8-689\] width (2) of port connection 'm_axi_arid' does not match port width (4) of module 'rfnoc_image_core' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:868\] WARNING: \[Synth 8-689\] width (64) of port connection 'm_axi_araddr' does not match port width (192) of module 'rfnoc_image_core' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:869\] WARNING: \[Synth 8-689\] width (16) of port connection 'm_axi_arlen' does not match port width (32) of module 'rfnoc_image_core' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:870\] WARNING: \[Synth 8-689\] width (6) of port connection 'm_axi_arsize' does not match port width (12) of module 'rfnoc_image_core' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:871\] WARNING: \[Synth 8-689\] width (4) of port connection 'm_axi_arburst' does not match port width (8) of module 'rfnoc_image_core' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:872\] WARNING: \[Synth 8-689\] width (2) of port connection 'm_axi_arlock' does not match port width (4) of module 'rfnoc_image_core' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:873\] WARNING: \[Synth 8-689\] width (8) of port connection 'm_axi_arcache' does not match port width (16) of module 'rfnoc_image_core' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:874\] WARNING: \[Synth 8-689\] width (6) of port connection 'm_axi_arprot' does not match port width (12) of module 'rfnoc_image_core' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:875\] WARNING: \[Synth 8-689\] width (8) of port connection 'm_axi_arqos' does not match port width (16) of module 'rfnoc_image_core' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:876\] WARNING: \[Synth 8-689\] width (8) of port connection 'm_axi_arregion' does not match port width (16) of module 'rfnoc_image_core' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:877\] WARNING: \[Synth 8-689\] width (2) of port connection 'm_axi_arvalid' does not match port width (4) of module 'rfnoc_image_core' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:879\] WARNING: \[Synth 8-689\] width (2) of port connection 'm_axi_rready' does not match port width (4) of module 'rfnoc_image_core' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_core.v:887\] WARNING: \[Synth 8-689\] width (32) of port connection 's_axi_awaddr' does not match port width (14) of module 'e31x_core' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x.v:893\] WARNING: \[Synth 8-689\] width (32) of port connection 's_axi_araddr' does not match port width (14) of module 'e31x_core' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x.v:906\] WARNING: \[Synth 8-689\] width (6) of port connection 'occupied' does not match port width (16) of module 'axi_fifo_bram__parameterized10' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/axi_pmu.v:167\] WARNING: \[Synth 8-689\] width (6) of port connection 'space' does not match port width (16) of module 'axi_fifo_bram__parameterized10' \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/axi_pmu.v:168\] \[00:01:14\] Current task: Synthesis +++ Current Phase: Starting CRITICAL WARNING: \[Netlist 29-160\] Cannot set property 'iostandard', because the property does not exist for objects of type 'pin'. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/e31x_ps_bd_processing_system7_0_0.xdc:405\] CRITICAL WARNING: \[Netlist 29-160\] Cannot set property 'PACKAGE_PIN', because the property does not exist for objects of type 'pin'. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/e31x_ps_bd_processing_system7_0_0.xdc:406\] CRITICAL WARNING: \[Netlist 29-160\] Cannot set property 'slew', because the property does not exist for objects of type 'pin'. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/e31x_ps_bd_processing_system7_0_0.xdc:407\] CRITICAL WARNING: \[Netlist 29-160\] Cannot set property 'PIO_DIRECTION', because the property does not exist for objects of type 'pin'. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/e31x_ps_bd_processing_system7_0_0.xdc:408\] CRITICAL WARNING: \[Netlist 29-160\] Cannot set property 'iostandard', because the property does not exist for objects of type 'pin'. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/e31x_ps_bd_processing_system7_0_0.xdc:417\] CRITICAL WARNING: \[Netlist 29-160\] Cannot set property 'PACKAGE_PIN', because the property does not exist for objects of type 'pin'. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/e31x_ps_bd_processing_system7_0_0.xdc:418\] CRITICAL WARNING: \[Netlist 29-160\] Cannot set property 'slew', because the property does not exist for objects of type 'pin'. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/e31x_ps_bd_processing_system7_0_0.xdc:419\] CRITICAL WARNING: \[Netlist 29-160\] Cannot set property 'PIO_DIRECTION', because the property does not exist for objects of type 'pin'. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/e31x_ps_bd_processing_system7_0_0.xdc:420\] WARNING: \[Vivado 12-4702\] slew is not a supported property on input port(s). Setting is ignored. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/e31x_ps_bd_processing_system7_0_0.xdc:691\] WARNING: \[Vivado 12-4702\] slew is not a supported property on input port(s). Setting is ignored. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/e31x_ps_bd_processing_system7_0_0.xdc:694\] WARNING: \[Vivado 12-4702\] slew is not a supported property on input port(s). Setting is ignored. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/e31x_ps_bd_processing_system7_0_0.xdc:697\] CRITICAL WARNING: \[Constraints 18-1056\] Clock 'bus_clk' completely overrides clock 'clk_fpga_0'. CRITICAL WARNING: \[Constraints 18-1056\] Clock 'clk40' completely overrides clock 'clk_fpga_1'. WARNING: \[Vivado 12-508\] No pins matched 'get_pins -hierarchical -filter {NAME =\~ \*/synchronizer_false_path/stages\[0\].value_reg\[0\]\[\*\]/S}'. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_timing.xdc:141\] WARNING: \[Project 1-498\] One or more constraints failed evaluation while reading constraint file \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_timing.xdc\] and the design contains unresolved black boxes. These constraints will be read post-synthesis (as long as their source constraint file is marked as used_in_implementation) and should be applied correctly then. You should review the constraints listed in the file \[.Xil/e31x_propImpl.xdc\] and check the run log file to verify that these constraints were correctly applied. WARNING: \[XPM_CDC_GRAY: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_GRAY: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_GRAY: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_GRAY: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_GRAY: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_GRAY: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_GRAY: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_GRAY: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_GRAY: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_GRAY: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[Vivado 12-180\] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3\] WARNING: \[Vivado 12-180\] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3\] WARNING: \[Vivado 12-180\] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3\] WARNING: \[Vivado 12-180\] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3\] WARNING: \[Vivado 12-180\] No cells matched 'get_cells -hier -filter {PRIMITIVE_SUBGROUP==LUTRAM || PRIMITIVE_SUBGROUP==dram || PRIMITIVE_SUBGROUP==uram || PRIMITIVE_SUBGROUP==BRAM}'. \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_memory/tcl/xpm_memory_xdc.tcl:3\] WARNING: \[Timing 38-316\] Clock period '10.000' specified during out-of-context synthesis of instance 'e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/ctrlport_endpoint_i/gen_async_fifos.in_fifo_i/fifo_section\[0\].impl_srl_i' at clock pin 'rd_clk' is different from the actual clock period '5.000', this can lead to different synthesis results. WARNING: \[Timing 38-316\] Clock period '10.000' specified during out-of-context synthesis of instance 'e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/ctrlport_endpoint_i/gen_async_fifos.out_fifo_i/fifo_section\[0\].impl_srl_i' at clock pin 'wr_clk' is different from the actual clock period '5.000', this can lead to different synthesis results. WARNING: \[Timing 38-316\] Clock period '10.000' specified during out-of-context synthesis of instance 'e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_input_in\[0\].chdr_to_axis_data_in_in/flush_2clk_ctrl_i/fifo_section\[0\].impl_srl_i' at clock pin 'rd_clk' is different from the actual clock period '5.000', this can lead to different synthesis results. WARNING: \[Timing 38-316\] Clock period '10.000' specified during out-of-context synthesis of instance 'e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_input_in\[0\].chdr_to_axis_data_in_in/gen_async_info_fifo.info_fifo_i/fifo_section\[0\].impl_srl_i' at clock pin 'rd_clk' is different from the actual clock period '5.000', this can lead to different synthesis results. WARNING: \[Timing 38-316\] Clock period '10.000' specified during out-of-context synthesis of instance 'e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_input_in\[0\].chdr_to_axis_data_in_in/gen_async_info_fifo.info_fifo_i/fifo_section\[1\].impl_srl_i' at clock pin 'rd_clk' is different from the actual clock period '5.000', this can lead to different synthesis results. WARNING: \[Timing 38-316\] Clock period '10.000' specified during out-of-context synthesis of instance 'e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_input_in\[0\].chdr_to_axis_data_in_in/no_gen_axis_width_conv.gen_async_pyld_fifo.pyld_fifo_i/fifo_section\[0\].impl_srl_i' at clock pin 'rd_clk' is different from the actual clock period '5.000', this can lead to different synthesis results. WARNING: \[Timing 38-316\] Clock period '10.000' specified during out-of-context synthesis of instance 'e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_input_in\[1\].chdr_to_axis_data_in_in/flush_2clk_ctrl_i/fifo_section\[0\].impl_srl_i' at clock pin 'rd_clk' is different from the actual clock period '5.000', this can lead to different synthesis results. WARNING: \[Timing 38-316\] Clock period '10.000' specified during out-of-context synthesis of instance 'e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_input_in\[1\].chdr_to_axis_data_in_in/gen_async_info_fifo.info_fifo_i/fifo_section\[0\].impl_srl_i' at clock pin 'rd_clk' is different from the actual clock period '5.000', this can lead to different synthesis results. WARNING: \[Timing 38-316\] Clock period '10.000' specified during out-of-context synthesis of instance 'e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_input_in\[1\].chdr_to_axis_data_in_in/gen_async_info_fifo.info_fifo_i/fifo_section\[1\].impl_srl_i' at clock pin 'rd_clk' is different from the actual clock period '5.000', this can lead to different synthesis results. WARNING: \[Timing 38-316\] Clock period '10.000' specified during out-of-context synthesis of instance 'e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_input_in\[1\].chdr_to_axis_data_in_in/no_gen_axis_width_conv.gen_async_pyld_fifo.pyld_fifo_i/fifo_section\[0\].impl_srl_i' at clock pin 'rd_clk' is different from the actual clock period '5.000', this can lead to different synthesis results. WARNING: \[Timing 38-316\] Clock period '10.000' specified during out-of-context synthesis of instance 'e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_output_out\[0\].axis_data_to_chdr_out_out/gen_async_info_fifo.pkt_info_fifo/fifo_section\[0\].impl_srl_i' at clock pin 'wr_clk' is different from the actual clock period '5.000', this can lead to different synthesis results. WARNING: \[Timing 38-316\] Clock period '10.000' specified during out-of-context synthesis of instance 'e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_output_out\[0\].axis_data_to_chdr_out_out/gen_async_info_fifo.pkt_info_fifo/fifo_section\[1\].impl_srl_i' at clock pin 'wr_clk' is different from the actual clock period '5.000', this can lead to different synthesis results. WARNING: \[Timing 38-316\] Clock period '10.000' specified during out-of-context synthesis of instance 'e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_output_out\[0\].axis_data_to_chdr_out_out/no_gen_axis_width_conv.gen_async_pyld_fifo.pyld_fifo/fifo_section\[0\].impl_bram_i' at clock pin 'wr_clk' is different from the actual clock period '5.000', this can lead to different synthesis results. WARNING: \[Timing 38-316\] Clock period '10.000' specified during out-of-context synthesis of instance 'e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_output_out\[1\].axis_data_to_chdr_out_out/gen_async_info_fifo.pkt_info_fifo/fifo_section\[0\].impl_srl_i' at clock pin 'wr_clk' is different from the actual clock period '5.000', this can lead to different synthesis results. WARNING: \[Timing 38-316\] Clock period '10.000' specified during out-of-context synthesis of instance 'e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_output_out\[1\].axis_data_to_chdr_out_out/gen_async_info_fifo.pkt_info_fifo/fifo_section\[1\].impl_srl_i' at clock pin 'wr_clk' is different from the actual clock period '5.000', this can lead to different synthesis results. WARNING: \[Timing 38-316\] Clock period '10.000' specified during out-of-context synthesis of instance 'e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_output_out\[1\].axis_data_to_chdr_out_out/no_gen_axis_width_conv.gen_async_pyld_fifo.pyld_fifo/fifo_section\[0\].impl_bram_i' at clock pin 'wr_clk' is different from the actual clock period '5.000', this can lead to different synthesis results. \[00:03:00\] Current task: Synthesis +++ Current Phase: Handling Custom Attributes \[00:03:01\] Current task: Synthesis +++ Current Phase: RTL Component Statistics \[00:03:01\] Current task: Synthesis +++ Current Phase: Part Resource Summary WARNING: \[Synth 8-7129\] Port rsta in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port regcea in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port injectsbiterra in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port injectdbiterra in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port clkb in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port regceb in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port web\[0\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[69\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[68\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[67\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[66\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[65\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[64\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[63\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[62\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[61\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[60\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[59\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[58\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[57\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[56\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[55\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[54\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[53\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[52\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[51\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[50\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[49\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[48\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[47\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[46\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[45\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[44\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[43\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[42\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[41\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[40\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[39\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[38\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[37\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[36\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[35\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[34\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[33\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[32\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[31\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[30\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[29\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[28\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[27\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[26\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[25\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[24\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[23\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[22\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[21\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[20\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[19\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[18\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[17\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[16\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[15\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[14\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[13\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[12\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[11\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[10\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[9\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[8\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[7\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[6\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[5\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[4\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[3\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[2\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[1\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port dinb\[0\] in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port injectsbiterrb in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port injectdbiterrb in module xpm_memory_base__parameterized5 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port s_sc_req\[0\] in module sc_node_v1_0_13_top__parameterized3 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port s_sc_info\[0\] in module sc_node_v1_0_13_top__parameterized3 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port s_sc_payld\[0\] in module sc_node_v1_0_13_top__parameterized3 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port m_sc_aclken in module sc_node_v1_0_13_top__parameterized3 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port m_axis_arb_tready in module sc_node_v1_0_13_top__parameterized3 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port s_axis_arb_tvalid in module sc_node_v1_0_13_top__parameterized3 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port s_axis_arb_tdata\[15\] in module sc_node_v1_0_13_top__parameterized3 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port s_axis_arb_tdata\[14\] in module sc_node_v1_0_13_top__parameterized3 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port s_axis_arb_tdata\[13\] in module sc_node_v1_0_13_top__parameterized3 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port s_axis_arb_tdata\[12\] in module sc_node_v1_0_13_top__parameterized3 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port s_axis_arb_tdata\[11\] in module sc_node_v1_0_13_top__parameterized3 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port s_axis_arb_tdata\[10\] in module sc_node_v1_0_13_top__parameterized3 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port s_axis_arb_tdata\[9\] in module sc_node_v1_0_13_top__parameterized3 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port s_axis_arb_tdata\[8\] in module sc_node_v1_0_13_top__parameterized3 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port s_axis_arb_tdata\[7\] in module sc_node_v1_0_13_top__parameterized3 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port s_axis_arb_tdata\[6\] in module sc_node_v1_0_13_top__parameterized3 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port s_axis_arb_tdata\[5\] in module sc_node_v1_0_13_top__parameterized3 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port s_axis_arb_tdata\[4\] in module sc_node_v1_0_13_top__parameterized3 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port s_axis_arb_tdata\[3\] in module sc_node_v1_0_13_top__parameterized3 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port s_axis_arb_tdata\[2\] in module sc_node_v1_0_13_top__parameterized3 is either unconnected or has no load WARNING: \[Synth 8-7129\] Port s_axis_arb_tdata\[1\] in module sc_node_v1_0_13_top__parameterized3 is either unconnected or has no load WARNING: \[Synth 8-6014\] Unused sequential element ingress_fifo_i/main_fifo/fifo_bram/ram/impl/ram_reg was removed. WARNING: \[Synth 8-6014\] Unused sequential element ingress_fifo_i/main_fifo/fifo_bram/ram/impl/ram_reg was removed. WARNING: \[Synth 8-6014\] Unused sequential element ingress_fifo_i/main_fifo/fifo_bram/ram/impl/ram_reg was removed. WARNING: \[Synth 8-6014\] Unused sequential element ingress_fifo_i/main_fifo/fifo_bram/ram/impl/ram_reg was removed. WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awid\[1\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awid\[0\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awsize\[5\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awsize\[4\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awsize\[3\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awsize\[2\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awsize\[1\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awsize\[0\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awburst\[3\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awburst\[2\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awburst\[1\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awburst\[0\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awlock\[1\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awlock\[0\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awcache\[7\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awcache\[6\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awcache\[5\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awcache\[4\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awcache\[3\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awcache\[2\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awcache\[1\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awcache\[0\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awprot\[5\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awprot\[4\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awprot\[3\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awprot\[2\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awprot\[1\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awprot\[0\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awqos\[7\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awqos\[6\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awqos\[5\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awqos\[4\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awqos\[3\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awqos\[2\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awqos\[1\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awqos\[0\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awregion\[7\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awregion\[6\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awregion\[5\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awregion\[4\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awregion\[3\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awregion\[2\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awregion\[1\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awregion\[0\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awuser\[1\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_awuser\[0\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_wstrb\[15\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_wstrb\[14\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_wstrb\[13\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_wstrb\[12\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_wstrb\[11\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_wstrb\[10\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_wstrb\[9\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_wstrb\[8\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_wstrb\[7\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_wstrb\[6\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_wstrb\[5\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_wstrb\[4\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_wstrb\[3\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_wstrb\[2\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_wstrb\[1\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_wstrb\[0\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_wuser\[1\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_wuser\[0\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arid\[1\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arid\[0\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arsize\[5\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arsize\[4\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arsize\[3\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arsize\[2\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arsize\[1\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arsize\[0\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arburst\[3\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arburst\[2\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arburst\[1\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arburst\[0\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arlock\[1\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arlock\[0\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arcache\[7\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arcache\[6\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arcache\[5\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arcache\[4\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arcache\[3\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arcache\[2\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arcache\[1\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arcache\[0\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arprot\[5\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arprot\[4\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arprot\[3\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arprot\[2\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arprot\[1\] driven by constant 1 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arprot\[0\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arqos\[7\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arqos\[6\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arqos\[5\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arqos\[4\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arqos\[3\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arqos\[2\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arqos\[1\] driven by constant 0 WARNING: \[Synth 8-3917\] design rfnoc_block_replay has port m_axi_arqos\[0\] driven by constant 0 WARNING: \[Synth 8-6014\] Unused sequential element rec_axi_fifo/fifo_bram/ram/impl/ram_reg was removed. WARNING: \[Synth 8-6014\] Unused sequential element play_axi_fifo/fifo_bram/ram/impl/ram_reg was removed. WARNING: \[Synth 8-6014\] Unused sequential element rec_axi_fifo/fifo_bram/ram/impl/ram_reg was removed. WARNING: \[Synth 8-6014\] Unused sequential element play_axi_fifo/fifo_bram/ram/impl/ram_reg was removed. WARNING: \[Synth 8-6014\] Unused sequential element no_gen_axis_width_conv.gen_async_pyld_fifo.pyld_fifo/ext_fifo_i/ram/impl/ram_reg was removed. WARNING: \[Synth 8-6014\] Unused sequential element no_gen_axis_width_conv.gen_async_pyld_fifo.pyld_fifo/ext_fifo_i/ram/impl/ram_reg was removed. WARNING: \[Synth 8-6014\] Unused sequential element gen_ctrl_slave.axis_ctrl_slv_i/gate_i/ram_i/impl/ram_reg was removed. WARNING: \[Synth 8-3936\] Found unconnected internal register 'ctrlport_timer_i/resp_cache_i/o_tdata_reg' and it is trimmed from '34' to '32' bits. \[/home/grcusrp/uhd/fpga/usrp3/lib/fifo/axi_fifo_flop.v:37\] WARNING: \[Synth 8-6014\] Unused sequential element gen_axis_width_conv.pyld_fifo_i/fifo_bram/ram/impl/ram_reg was removed. WARNING: \[Synth 8-6014\] Unused sequential element gen_axis_width_conv.pyld_fifo_i/fifo_bram/ram/impl/ram_reg was removed. WARNING: \[Synth 8-6014\] Unused sequential element gen_axis_width_conv.pyld_fifo/fifo_bram/ram/impl/ram_reg was removed. WARNING: \[Synth 8-6014\] Unused sequential element gen_axis_width_conv.pyld_fifo/fifo_bram/ram/impl/ram_reg was removed. WARNING: \[Synth 8-6014\] Unused sequential element gen_ctrl_slave.slv_fifo_i/fifo_bram/ram/impl/ram_reg was removed. WARNING: \[Synth 8-6014\] Unused sequential element gen_ctrl_slave.axis_ctrl_slv_i/gate_i/ram_i/impl/ram_reg was removed. WARNING: \[Synth 8-3936\] Found unconnected internal register 'dest_mux_i/axi_fifo/fifo_flop2/o_tdata_reg' and it is trimmed from '5' to '4' bits. \[/home/grcusrp/uhd/fpga/usrp3/lib/fifo/axi_fifo_flop2.v:38\] WARNING: \[Synth 8-3936\] Found unconnected internal register 'dest_mux_i/axi_fifo/fifo_flop2/o_tdata_reg' and it is trimmed from '5' to '4' bits. \[/home/grcusrp/uhd/fpga/usrp3/lib/fifo/axi_fifo_flop2.v:38\] WARNING: \[Synth 8-3936\] Found unconnected internal register 'dest_mux_i/axi_fifo/fifo_flop2/o_tdata_reg' and it is trimmed from '5' to '4' bits. \[/home/grcusrp/uhd/fpga/usrp3/lib/fifo/axi_fifo_flop2.v:38\] WARNING: \[Synth 8-3936\] Found unconnected internal register 'dest_mux_i/axi_fifo/fifo_flop2/o_tdata_reg' and it is trimmed from '5' to '4' bits. \[/home/grcusrp/uhd/fpga/usrp3/lib/fifo/axi_fifo_flop2.v:38\] WARNING: \[Synth 8-3936\] Found unconnected internal register 'dest_mux_i/axi_fifo/fifo_flop2/o_tdata_reg' and it is trimmed from '5' to '4' bits. \[/home/grcusrp/uhd/fpga/usrp3/lib/fifo/axi_fifo_flop2.v:38\] WARNING: \[Synth 8-6014\] Unused sequential element axi_packet_gate_i/ram_i/impl/ram_reg was removed. WARNING: \[Synth 8-6014\] Unused sequential element axi_packet_gate_i/ram_i/impl/ram_reg was removed. WARNING: \[Synth 8-6014\] Unused sequential element axi_packet_gate_i/ram_i/impl/ram_reg was removed. WARNING: \[Synth 8-6014\] Unused sequential element axi_packet_gate_i/ram_i/impl/ram_reg was removed. WARNING: \[Synth 8-6014\] Unused sequential element axi_packet_gate_i/ram_i/impl/ram_reg was removed. WARNING: \[Synth 8-6014\] Unused sequential element kv_map_i/map_i/mem_i/impl/ram_reg was removed. WARNING: \[Synth 8-3936\] Found unconnected internal register 'ppslp/coarse_reg' and it is trimmed from '28' to '16' bits. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/ppsloop.v:243\] WARNING: \[Synth 8-6014\] Unused sequential element cpu_out_gate_i/ram_i/impl/ram_reg was removed. WARNING: \[Synth 8-6014\] Unused sequential element chdr_user_fifo_i/fifo_bram/ram/impl/ram_reg was removed. WARNING: \[Synth 8-6014\] Unused sequential element chdr_out_gate_i/ram_i/impl/ram_reg was removed. WARNING: \[Synth 8-6014\] Unused sequential element chdr_out_gate_i/addr_fifo_i/fifo_bram/ram/impl/ram_reg was removed. WARNING: \[Synth 8-6014\] Unused sequential element kv_map_i/mem_i/impl/ram_reg was removed. WARNING: \[Synth 8-6014\] Unused sequential element eth_adapter_i/cpu_fifo_i/fifo_bram/ram/impl/ram_reg was removed. WARNING: \[Synth 8-6014\] Unused sequential element eth_adapter_i/chdr_fifo_i/fifo_bram/ram/impl/ram_reg was removed. WARNING: \[Synth 8-6014\] Unused sequential element inst_axi_pmu/axi_fifo_short_inst/ram/impl/ram_reg was removed. \[00:04:36\] Current task: Synthesis +++ Current Phase: Cross Boundary and Area Optimization \[00:04:42\] Current task: Synthesis +++ Current Phase: Applying XDC Timing Constraints \[00:05:26\] Current task: Synthesis +++ Current Phase: Timing Optimization \[00:06:11\] Current task: Synthesis +++ Current Phase: Technology Mapping \[00:06:12\] Current task: Synthesis +++ Current Phase: IO Insertion \[00:06:14\] Current task: Synthesis +++ Current Phase: Flattening Before IO Insertion WARNING: \[Synth 8-3295\] tying undriven pin I_AXI_DMA_REG_MODULE/strm_valid_int2_inferred:in0 to constant 0 WARNING: \[Synth 8-3295\] tying undriven pin I_AXI_DMA_REG_MODULE/strm_valid_int_cdc_to_inferred:in0 to constant 0 \[00:06:28\] Current task: Synthesis +++ Current Phase: Final Netlist Cleanup WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/ipshared/7ee4/hdl/axi_clock_converter_v2_1_vl_rfs.v:543\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/ipshared/7ee4/hdl/axi_clock_converter_v2_1_vl_rfs.v:555\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/ipshared/7ee4/hdl/axi_clock_converter_v2_1_vl_rfs.v:544\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/ipshared/7ee4/hdl/axi_clock_converter_v2_1_vl_rfs.v:599\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/ipshared/7ee4/hdl/axi_clock_converter_v2_1_vl_rfs.v:544\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/ipshared/7ee4/hdl/axi_clock_converter_v2_1_vl_rfs.v:556\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/ipshared/7ee4/hdl/axi_clock_converter_v2_1_vl_rfs.v:556\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:583\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:221\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:221\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:221\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/ipshared/7ee4/hdl/axi_clock_converter_v2_1_vl_rfs.v:600\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/ipshared/7ee4/hdl/axi_clock_converter_v2_1_vl_rfs.v:600\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:594\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:221\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:221\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:221\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:594\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:221\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:221\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:221\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/ipshared/7ee4/hdl/axi_clock_converter_v2_1_vl_rfs.v:600\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/ipshared/7ee4/hdl/axi_clock_converter_v2_1_vl_rfs.v:600\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:594\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:221\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:221\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:221\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:592\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/ipshared/7ee4/hdl/axi_clock_converter_v2_1_vl_rfs.v:600\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_inter_2x64_128_bd/axi_inter_2x64_128_bd/ipshared/7ee4/hdl/axi_clock_converter_v2_1_vl_rfs.v:600\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:583\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:221\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:221\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:221\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:588\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:588\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:588\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:588\] WARNING: \[Synth 8-5396\] Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv:588\] \[00:06:37\] Current task: Synthesis +++ Current Phase: Renaming Generated Instances \[00:06:44\] Current task: Synthesis +++ Current Phase: Rebuilding User Hierarchy \[00:06:48\] Current task: Synthesis +++ Current Phase: Renaming Generated Ports \[00:06:48\] Current task: Synthesis +++ Current Phase: Handling Custom Attributes \[00:06:48\] Current task: Synthesis +++ Current Phase: Renaming Generated Nets \[00:06:53\] Current task: Synthesis +++ Current Phase: Writing Synthesis Report \[00:06:53\] Current task: Synthesis +++ Current Phase: Finished \[00:06:53\] Translating Synthesized Netlist CRITICAL WARNING: \[Designutils 20-1280\] Could not find module 'axi_hb31'. The XDC file /home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_hb31/constraints/fir_compiler_v7_2.xdc will not be read for any cell of this module. CRITICAL WARNING: \[Designutils 20-1280\] Could not find module 'axi_hb47'. The XDC file /home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/axi_hb47/constraints/fir_compiler_v7_2.xdc will not be read for any cell of this module. WARNING: \[Vivado_Tcl 4-919\] Waiver ID 'CDC-1' -from list should not be empty. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_axi_dma_eth_internal_0/e31x_ps_bd_axi_dma_eth_internal_0.xdc:61\] CRITICAL WARNING: \[Netlist 29-160\] Cannot set property 'iostandard', because the property does not exist for objects of type 'pin'. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/e31x_ps_bd_processing_system7_0_0.xdc:405\] CRITICAL WARNING: \[Netlist 29-160\] Cannot set property 'PACKAGE_PIN', because the property does not exist for objects of type 'pin'. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/e31x_ps_bd_processing_system7_0_0.xdc:406\] CRITICAL WARNING: \[Netlist 29-160\] Cannot set property 'slew', because the property does not exist for objects of type 'pin'. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/e31x_ps_bd_processing_system7_0_0.xdc:407\] CRITICAL WARNING: \[Netlist 29-160\] Cannot set property 'PIO_DIRECTION', because the property does not exist for objects of type 'pin'. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/e31x_ps_bd_processing_system7_0_0.xdc:408\] CRITICAL WARNING: \[Netlist 29-160\] Cannot set property 'iostandard', because the property does not exist for objects of type 'pin'. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/e31x_ps_bd_processing_system7_0_0.xdc:417\] CRITICAL WARNING: \[Netlist 29-160\] Cannot set property 'PACKAGE_PIN', because the property does not exist for objects of type 'pin'. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/e31x_ps_bd_processing_system7_0_0.xdc:418\] CRITICAL WARNING: \[Netlist 29-160\] Cannot set property 'slew', because the property does not exist for objects of type 'pin'. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/e31x_ps_bd_processing_system7_0_0.xdc:419\] CRITICAL WARNING: \[Netlist 29-160\] Cannot set property 'PIO_DIRECTION', because the property does not exist for objects of type 'pin'. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/e31x_ps_bd_processing_system7_0_0.xdc:420\] WARNING: \[Vivado 12-4702\] slew is not a supported property on input port(s). Setting is ignored. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/e31x_ps_bd_processing_system7_0_0.xdc:691\] WARNING: \[Vivado 12-4702\] slew is not a supported property on input port(s). Setting is ignored. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/e31x_ps_bd_processing_system7_0_0.xdc:694\] WARNING: \[Vivado 12-4702\] slew is not a supported property on input port(s). Setting is ignored. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_processing_system7_0_0/e31x_ps_bd_processing_system7_0_0.xdc:697\] CRITICAL WARNING: \[Constraints 18-1055\] Clock 'bus_clk' completely overrides clock 'clk_fpga_0', which is referenced by one or more other constraints. Any constraints that refer to the overridden clock will be ignored. CRITICAL WARNING: \[Constraints 18-1055\] Clock 'clk40' completely overrides clock 'clk_fpga_1', which is referenced by one or more other constraints. Any constraints that refer to the overridden clock will be ignored. WARNING: \[Vivado 12-2489\] -input_jitter contains time 1.628100 which will be rounded to 1.628 to ensure it is an integer multiple of 1 picosecond \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/e31x_timing.xdc:47\] WARNING: \[Vivado 12-830\] No fanout objects found for 'all_fanout -from \[get_ports -scoped_to_current_instance m_axi_aclk\] -flat -endpoints_only -only_cells'. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_auto_cc_4/e31x_ps_bd_auto_cc_4_clocks.xdc:17\] WARNING: \[Vivado_Tcl 4-921\] Waiver ID 'CDC-10' -to list should not be empty. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_auto_cc_0/e31x_ps_bd_auto_cc_0_clocks.xdc:7\] WARNING: \[Vivado_Tcl 4-921\] Waiver ID 'CDC-11' -to list should not be empty. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_auto_cc_0/e31x_ps_bd_auto_cc_0_clocks.xdc:10\] WARNING: \[Vivado_Tcl 4-921\] Waiver ID 'CDC-15' -to list should not be empty. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_auto_cc_0/e31x_ps_bd_auto_cc_0_clocks.xdc:13\] WARNING: \[Vivado_Tcl 4-939\] Waiver ID 'LUTAR-1' object list should not be empty (perhaps an invalid wildcard was used or only unsupported objects). \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_auto_cc_0/e31x_ps_bd_auto_cc_0_clocks.xdc:17\] WARNING: \[Vivado_Tcl 4-921\] Waiver ID 'CDC-10' -to list should not be empty. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_auto_cc_1/e31x_ps_bd_auto_cc_1_clocks.xdc:7\] WARNING: \[Vivado_Tcl 4-921\] Waiver ID 'CDC-11' -to list should not be empty. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_auto_cc_1/e31x_ps_bd_auto_cc_1_clocks.xdc:10\] WARNING: \[Vivado_Tcl 4-921\] Waiver ID 'CDC-15' -to list should not be empty. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_auto_cc_1/e31x_ps_bd_auto_cc_1_clocks.xdc:13\] WARNING: \[Vivado_Tcl 4-939\] Waiver ID 'LUTAR-1' object list should not be empty (perhaps an invalid wildcard was used or only unsupported objects). \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_auto_cc_1/e31x_ps_bd_auto_cc_1_clocks.xdc:17\] WARNING: \[Vivado_Tcl 4-921\] Waiver ID 'CDC-10' -to list should not be empty. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_auto_cc_2/e31x_ps_bd_auto_cc_2_clocks.xdc:7\] WARNING: \[Vivado_Tcl 4-921\] Waiver ID 'CDC-11' -to list should not be empty. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_auto_cc_2/e31x_ps_bd_auto_cc_2_clocks.xdc:10\] WARNING: \[Vivado_Tcl 4-921\] Waiver ID 'CDC-15' -to list should not be empty. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_auto_cc_2/e31x_ps_bd_auto_cc_2_clocks.xdc:13\] WARNING: \[Vivado_Tcl 4-939\] Waiver ID 'LUTAR-1' object list should not be empty (perhaps an invalid wildcard was used or only unsupported objects). \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_auto_cc_2/e31x_ps_bd_auto_cc_2_clocks.xdc:17\] WARNING: \[Vivado_Tcl 4-921\] Waiver ID 'CDC-10' -to list should not be empty. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_auto_cc_3/e31x_ps_bd_auto_cc_3_clocks.xdc:7\] WARNING: \[Vivado_Tcl 4-921\] Waiver ID 'CDC-11' -to list should not be empty. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_auto_cc_3/e31x_ps_bd_auto_cc_3_clocks.xdc:10\] WARNING: \[Vivado_Tcl 4-921\] Waiver ID 'CDC-15' -to list should not be empty. \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_auto_cc_3/e31x_ps_bd_auto_cc_3_clocks.xdc:13\] WARNING: \[Vivado_Tcl 4-939\] Waiver ID 'LUTAR-1' object list should not be empty (perhaps an invalid wildcard was used or only unsupported objects). \[/home/grcusrp/uhd/fpga/usrp3/top/e31x/build-ip/xc7z020clg484-3/e31x_ps_bd/e31x_ps_bd/ip/e31x_ps_bd_auto_cc_3/e31x_ps_bd_auto_cc_3_clocks.xdc:17\] WARNING: \[XPM_CDC_GRAY: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_GRAY: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_GRAY: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_GRAY: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_GRAY: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_GRAY: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_GRAY: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_GRAY: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_GRAY: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_GRAY: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[Vivado_Tcl 4-919\] Waiver ID 'CDC-15' -from list should not be empty. \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl:30\] WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[Vivado_Tcl 4-919\] Waiver ID 'CDC-15' -from list should not be empty. \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl:30\] WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[Vivado_Tcl 4-919\] Waiver ID 'CDC-15' -from list should not be empty. \[/tools/Xilinx/Vivado/2021.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_handshake.tcl:30\] WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_HANDSHAKE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[XPM_CDC_SINGLE: TCL-1000\] The source and destination clocks are the same. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[0\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[10\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[11\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[12\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[13\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[14\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[15\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[16\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[17\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[18\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[19\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[1\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[20\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[21\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[22\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[23\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[24\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[25\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[26\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[27\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[28\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[29\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[2\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[30\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[31\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[3\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[4\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[5\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[6\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[7\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[8\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[9\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[0\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[16\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[17\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[18\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[19\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[1\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[20\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[21\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[22\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[23\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[24\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[25\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[26\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[27\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[28\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[29\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[2\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[30\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[31\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[0\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[10\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[11\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[12\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[13\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[14\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[15\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[16\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[17\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[18\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[19\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[1\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[20\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[21\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[22\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[23\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[24\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[25\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[26\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[27\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[28\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[29\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[2\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[30\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[31\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[3\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[4\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[5\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[6\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[7\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[8\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[9\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_out_iob_reg\[0\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_out_iob_reg\[16\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_out_iob_reg\[17\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_out_iob_reg\[18\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_out_iob_reg\[19\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_out_iob_reg\[1\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_out_iob_reg\[20\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_out_iob_reg\[21\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_out_iob_reg\[22\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_out_iob_reg\[23\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_out_iob_reg\[24\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_out_iob_reg\[25\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_out_iob_reg\[26\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_out_iob_reg\[27\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_out_iob_reg\[28\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_out_iob_reg\[29\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. WARNING: \[Constraints 18-5572\] Instance genblk2\[1\].gpio_atr_db_inst/gpio_out_iob_reg\[2\] has IOB constraint set, However, the instance does not seem to have valid I/O connection to be placed into I/O. The constraint on the instance will be ignored. \[00:08:11\] Current task: Translating Synthesized Netlist +++ Current Phase: Starting \[00:08:11\] Current task: Translating Synthesized Netlist +++ Current Phase: Finished \[00:08:11\] Executing Tcl: report_drc -ruledeck methodology_checks -file /home/grcusrp/uhd/fpga/usrp3/top/e31x/build-E310_SG3/methodology.rpt \[00:08:11\] Starting DRC Command \[00:08:53\] Current task: DRC +++ Current Phase: Starting \[00:08:53\] Current task: DRC +++ Current Phase: Finished \[00:08:53\] Executing Tcl: opt_design -directive Default \[00:08:53\] Starting Logic Optimization Command \[00:08:53\] Current task: Logic Optimization +++ Current Phase: Starting \[00:08:53\] Current task: Logic Optimization +++ Current Phase: Finished \[00:08:53\] Starting DRC Task \[00:08:54\] Current task: DRC +++ Current Phase: Starting \[00:08:54\] Current task: DRC +++ Current Phase: Finished \[00:08:54\] Starting Cache Timing Information Task \[00:09:01\] Current task: Cache Timing Information +++ Current Phase: Starting \[00:09:02\] Current task: Cache Timing Information +++ Current Phase: Finished \[00:09:02\] Starting Logic Optimization Task \[00:09:06\] Current task: Logic Optimization +++ Current Phase: Starting \[00:09:09\] Current task: Logic Optimization +++ Current Phase: 1 Retarget \[00:09:10\] Current task: Logic Optimization +++ Current Phase: 2 Constant propagation \[00:09:16\] Current task: Logic Optimization +++ Current Phase: 3 Sweep \[00:09:17\] Current task: Logic Optimization +++ Current Phase: 4 BUFG optimization \[00:09:18\] Current task: Logic Optimization +++ Current Phase: 5 Shift Register Optimization \[00:09:19\] Current task: Logic Optimization +++ Current Phase: 6 Post Processing Netlist \[00:09:20\] Current task: Logic Optimization +++ Current Phase: Finished \[00:09:20\] Starting Connectivity Check Task \[00:09:20\] Current task: Connectivity Check +++ Current Phase: Starting \[00:09:21\] Current task: Connectivity Check +++ Current Phase: Finished \[00:09:21\] Starting Power Optimization Task \[00:09:44\] Current task: Power Optimization +++ Current Phase: Starting \[00:09:44\] Current task: Power Optimization +++ Current Phase: Finished \[00:09:44\] Starting PowerOpt Patch Enables Task \[00:09:45\] Current task: PowerOpt Patch Enables +++ Current Phase: Starting \[00:09:45\] Current task: PowerOpt Patch Enables +++ Current Phase: Finished \[00:09:45\] Starting Final Cleanup Task \[00:09:47\] Current task: Final Cleanup +++ Current Phase: Starting \[00:09:47\] Current task: Final Cleanup +++ Current Phase: Finished \[00:09:47\] Starting Logic Optimization Task \[00:09:58\] Current task: Logic Optimization +++ Current Phase: Starting \[00:09:58\] Current task: Logic Optimization +++ Current Phase: Finished \[00:09:58\] Starting Netlist Obfuscation Task \[00:09:58\] Current task: Netlist Obfuscation +++ Current Phase: Starting \[00:09:58\] Current task: Netlist Obfuscation +++ Current Phase: Finished \[00:09:58\] Executing Tcl: place_design -directive Default \[00:09:58\] Starting Placer Command \[00:10:15\] Current task: Placer +++ Current Phase: Starting WARNING: \[DRC CHECK-3\] Report rule limit reached: REQP-1839 rule limit reached: 20 violations have been found. WARNING: \[DRC REQP-1839\] RAMB36 async control check: The RAMB36E1 e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_input_in\[0\].chdr_to_axis_data_in_in/gen_axis_width_conv.pyld_fifo_i/fifo_bram/ram/impl/ram_reg_0 has an input control pin e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_input_in\[0\].chdr_to_axis_data_in_in/gen_axis_width_conv.pyld_fifo_i/fifo_bram/ram/impl/ram_reg_0/ENBWREN (net: e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_input_in\[0\].chdr_to_axis_data_in_in/gen_axis_width_conv.pyld_fifo_i/fifo_bram/ram/impl/enb0) which is driven by a register (e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_input_in\[0\].chdr_to_axis_data_in_in/gen_axis_width_conv.payload_width_conv_i/fifo_i/fifo_section\[0\].impl_srl_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: \[DRC REQP-1839\] RAMB36 async control check: The RAMB36E1 e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_input_in\[0\].chdr_to_axis_data_in_in/gen_axis_width_conv.pyld_fifo_i/fifo_bram/ram/impl/ram_reg_1 has an input control pin e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_input_in\[0\].chdr_to_axis_data_in_in/gen_axis_width_conv.pyld_fifo_i/fifo_bram/ram/impl/ram_reg_1/ENBWREN (net: e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_input_in\[0\].chdr_to_axis_data_in_in/gen_axis_width_conv.pyld_fifo_i/fifo_bram/ram/impl/enb0) which is driven by a register (e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_input_in\[0\].chdr_to_axis_data_in_in/gen_axis_width_conv.payload_width_conv_i/fifo_i/fifo_section\[0\].impl_srl_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: \[DRC REQP-1839\] RAMB36 async control check: The RAMB36E1 e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_input_in\[1\].chdr_to_axis_data_in_in/gen_axis_width_conv.pyld_fifo_i/fifo_bram/ram/impl/ram_reg_0 has an input control pin e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_input_in\[1\].chdr_to_axis_data_in_in/gen_axis_width_conv.pyld_fifo_i/fifo_bram/ram/impl/ram_reg_0/ENBWREN (net: e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_input_in\[1\].chdr_to_axis_data_in_in/gen_axis_width_conv.pyld_fifo_i/fifo_bram/ram/impl/enb0) which is driven by a register (e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_input_in\[1\].chdr_to_axis_data_in_in/gen_axis_width_conv.payload_width_conv_i/fifo_i/fifo_section\[0\].impl_srl_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: \[DRC REQP-1839\] RAMB36 async control check: The RAMB36E1 e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_input_in\[1\].chdr_to_axis_data_in_in/gen_axis_width_conv.pyld_fifo_i/fifo_bram/ram/impl/ram_reg_1 has an input control pin e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_input_in\[1\].chdr_to_axis_data_in_in/gen_axis_width_conv.pyld_fifo_i/fifo_bram/ram/impl/ram_reg_1/ENBWREN (net: e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_input_in\[1\].chdr_to_axis_data_in_in/gen_axis_width_conv.pyld_fifo_i/fifo_bram/ram/impl/enb0) which is driven by a register (e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_input_in\[1\].chdr_to_axis_data_in_in/gen_axis_width_conv.payload_width_conv_i/fifo_i/fifo_section\[0\].impl_srl_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: \[DRC REQP-1839\] RAMB36 async control check: The RAMB36E1 e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_output_out\[0\].axis_data_to_chdr_out_out/gen_axis_width_conv.pyld_fifo/fifo_bram/ram/impl/ram_reg_0 has an input control pin e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_output_out\[0\].axis_data_to_chdr_out_out/gen_axis_width_conv.pyld_fifo/fifo_bram/ram/impl/ram_reg_0/ENARDEN (net: e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_output_out\[0\].axis_data_to_chdr_out_out/gen_axis_width_conv.pyld_fifo/fifo_bram/ram/impl/E\[0\]) which is driven by a register (e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_output_out\[0\].axis_data_to_chdr_out_out/gen_axis_width_conv.payload_width_conv_i/fifo_i/fifo_section\[0\].impl_srl_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: \[DRC REQP-1839\] RAMB36 async control check: The RAMB36E1 e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_output_out\[0\].axis_data_to_chdr_out_out/gen_axis_width_conv.pyld_fifo/fifo_bram/ram/impl/ram_reg_1 has an input control pin e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_output_out\[0\].axis_data_to_chdr_out_out/gen_axis_width_conv.pyld_fifo/fifo_bram/ram/impl/ram_reg_1/ENARDEN (net: e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_output_out\[0\].axis_data_to_chdr_out_out/gen_axis_width_conv.pyld_fifo/fifo_bram/ram/impl/E\[0\]) which is driven by a register (e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_output_out\[0\].axis_data_to_chdr_out_out/gen_axis_width_conv.payload_width_conv_i/fifo_i/fifo_section\[0\].impl_srl_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: \[DRC REQP-1839\] RAMB36 async control check: The RAMB36E1 e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_output_out\[0\].axis_data_to_chdr_out_out/gen_axis_width_conv.pyld_fifo/fifo_bram/ram/impl/ram_reg_2 has an input control pin e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_output_out\[0\].axis_data_to_chdr_out_out/gen_axis_width_conv.pyld_fifo/fifo_bram/ram/impl/ram_reg_2/ENARDEN (net: e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_output_out\[0\].axis_data_to_chdr_out_out/gen_axis_width_conv.pyld_fifo/fifo_bram/ram/impl/E\[0\]) which is driven by a register (e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_output_out\[0\].axis_data_to_chdr_out_out/gen_axis_width_conv.payload_width_conv_i/fifo_i/fifo_section\[0\].impl_srl_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: \[DRC REQP-1839\] RAMB36 async control check: The RAMB36E1 e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_output_out\[0\].axis_data_to_chdr_out_out/gen_axis_width_conv.pyld_fifo/fifo_bram/ram/impl/ram_reg_3 has an input control pin e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_output_out\[0\].axis_data_to_chdr_out_out/gen_axis_width_conv.pyld_fifo/fifo_bram/ram/impl/ram_reg_3/ENARDEN (net: e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_output_out\[0\].axis_data_to_chdr_out_out/gen_axis_width_conv.pyld_fifo/fifo_bram/ram/impl/E\[0\]) which is driven by a register (e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_output_out\[0\].axis_data_to_chdr_out_out/gen_axis_width_conv.payload_width_conv_i/fifo_i/fifo_section\[0\].impl_srl_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: \[DRC REQP-1839\] RAMB36 async control check: The RAMB36E1 e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_output_out\[1\].axis_data_to_chdr_out_out/gen_axis_width_conv.pyld_fifo/fifo_bram/ram/impl/ram_reg_0 has an input control pin e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_output_out\[1\].axis_data_to_chdr_out_out/gen_axis_width_conv.pyld_fifo/fifo_bram/ram/impl/ram_reg_0/ENARDEN (net: e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_output_out\[1\].axis_data_to_chdr_out_out/gen_axis_width_conv.pyld_fifo/fifo_bram/ram/impl/E\[0\]) which is driven by a register (e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_output_out\[1\].axis_data_to_chdr_out_out/gen_axis_width_conv.payload_width_conv_i/fifo_i/fifo_section\[0\].impl_srl_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: \[DRC REQP-1839\] RAMB36 async control check: The RAMB36E1 e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_output_out\[1\].axis_data_to_chdr_out_out/gen_axis_width_conv.pyld_fifo/fifo_bram/ram/impl/ram_reg_1 has an input control pin e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_output_out\[1\].axis_data_to_chdr_out_out/gen_axis_width_conv.pyld_fifo/fifo_bram/ram/impl/ram_reg_1/ENARDEN (net: e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_output_out\[1\].axis_data_to_chdr_out_out/gen_axis_width_conv.pyld_fifo/fifo_bram/ram/impl/E\[0\]) which is driven by a register (e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_output_out\[1\].axis_data_to_chdr_out_out/gen_axis_width_conv.payload_width_conv_i/fifo_i/fifo_section\[0\].impl_srl_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: \[DRC REQP-1839\] RAMB36 async control check: The RAMB36E1 e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_output_out\[1\].axis_data_to_chdr_out_out/gen_axis_width_conv.pyld_fifo/fifo_bram/ram/impl/ram_reg_2 has an input control pin e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_output_out\[1\].axis_data_to_chdr_out_out/gen_axis_width_conv.pyld_fifo/fifo_bram/ram/impl/ram_reg_2/ENARDEN (net: e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_output_out\[1\].axis_data_to_chdr_out_out/gen_axis_width_conv.pyld_fifo/fifo_bram/ram/impl/E\[0\]) which is driven by a register (e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_output_out\[1\].axis_data_to_chdr_out_out/gen_axis_width_conv.payload_width_conv_i/fifo_i/fifo_section\[0\].impl_srl_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: \[DRC REQP-1839\] RAMB36 async control check: The RAMB36E1 e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_output_out\[1\].axis_data_to_chdr_out_out/gen_axis_width_conv.pyld_fifo/fifo_bram/ram/impl/ram_reg_3 has an input control pin e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_output_out\[1\].axis_data_to_chdr_out_out/gen_axis_width_conv.pyld_fifo/fifo_bram/ram/impl/ram_reg_3/ENARDEN (net: e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_output_out\[1\].axis_data_to_chdr_out_out/gen_axis_width_conv.pyld_fifo/fifo_bram/ram/impl/E\[0\]) which is driven by a register (e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/gen_output_out\[1\].axis_data_to_chdr_out_out/gen_axis_width_conv.payload_width_conv_i/fifo_i/fifo_section\[0\].impl_srl_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: \[DRC REQP-1839\] RAMB36 async control check: The RAMB36E1 e31x_core_inst/rfnoc_image_core_i/b_replay0_1/gen_replay_blocks\[0\].axis_replay_i/play_axi_fifo/fifo_bram/ram/impl/ram_reg has an input control pin e31x_core_inst/rfnoc_image_core_i/b_replay0_1/gen_replay_blocks\[0\].axis_replay_i/play_axi_fifo/fifo_bram/ram/impl/ram_reg/ENARDEN (net: e31x_core_inst/rfnoc_image_core_i/b_replay0_1/gen_replay_blocks\[0\].axis_replay_i/play_axi_fifo/fifo_bram/ram/impl/enb0) which is driven by a register (e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_output_out\[0\].axis_data_to_chdr_out_out/no_gen_axis_width_conv.gen_async_pyld_fifo.pyld_fifo/fifo_section\[0\].impl_bram_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: \[DRC REQP-1839\] RAMB36 async control check: The RAMB36E1 e31x_core_inst/rfnoc_image_core_i/b_replay0_1/gen_replay_blocks\[1\].axis_replay_i/play_axi_fifo/fifo_bram/ram/impl/ram_reg has an input control pin e31x_core_inst/rfnoc_image_core_i/b_replay0_1/gen_replay_blocks\[1\].axis_replay_i/play_axi_fifo/fifo_bram/ram/impl/ram_reg/ENARDEN (net: e31x_core_inst/rfnoc_image_core_i/b_replay0_1/gen_replay_blocks\[1\].axis_replay_i/play_axi_fifo/fifo_bram/ram/impl/enb0) which is driven by a register (e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_output_out\[1\].axis_data_to_chdr_out_out/no_gen_axis_width_conv.gen_async_pyld_fifo.pyld_fifo/fifo_section\[0\].impl_bram_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: \[DRC REQP-1839\] RAMB36 async control check: The RAMB36E1 e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_output_out\[0\].axis_data_to_chdr_out_out/no_gen_axis_width_conv.gen_async_pyld_fifo.pyld_fifo/fifo_section\[0\].impl_bram_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop\[0\].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram has an input control pin e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_output_out\[0\].axis_data_to_chdr_out_out/no_gen_axis_width_conv.gen_async_pyld_fifo.pyld_fifo/fifo_section\[0\].impl_bram_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop\[0\].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram/ADDRARDADDR\[10\] (net: e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_output_out\[0\].axis_data_to_chdr_out_out/no_gen_axis_width_conv.gen_async_pyld_fifo.pyld_fifo/fifo_section\[0\].impl_bram_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop\[0\].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_0\[4\]) which is driven by a register (e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_output_out\[0\].axis_data_to_chdr_out_out/no_gen_axis_width_conv.gen_async_pyld_fifo.pyld_fifo/fifo_section\[0\].impl_bram_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg\[4\]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: \[DRC REQP-1839\] RAMB36 async control check: The RAMB36E1 e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_output_out\[0\].axis_data_to_chdr_out_out/no_gen_axis_width_conv.gen_async_pyld_fifo.pyld_fifo/fifo_section\[0\].impl_bram_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop\[0\].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram has an input control pin e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_output_out\[0\].axis_data_to_chdr_out_out/no_gen_axis_width_conv.gen_async_pyld_fifo.pyld_fifo/fifo_section\[0\].impl_bram_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop\[0\].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram/ADDRARDADDR\[11\] (net: e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_output_out\[0\].axis_data_to_chdr_out_out/no_gen_axis_width_conv.gen_async_pyld_fifo.pyld_fifo/fifo_section\[0\].impl_bram_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop\[0\].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_0\[5\]) which is driven by a register (e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_output_out\[0\].axis_data_to_chdr_out_out/no_gen_axis_width_conv.gen_async_pyld_fifo.pyld_fifo/fifo_section\[0\].impl_bram_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg\[5\]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: \[DRC REQP-1839\] RAMB36 async control check: The RAMB36E1 e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_output_out\[0\].axis_data_to_chdr_out_out/no_gen_axis_width_conv.gen_async_pyld_fifo.pyld_fifo/fifo_section\[0\].impl_bram_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop\[0\].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram has an input control pin e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_output_out\[0\].axis_data_to_chdr_out_out/no_gen_axis_width_conv.gen_async_pyld_fifo.pyld_fifo/fifo_section\[0\].impl_bram_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop\[0\].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram/ADDRARDADDR\[12\] (net: e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_output_out\[0\].axis_data_to_chdr_out_out/no_gen_axis_width_conv.gen_async_pyld_fifo.pyld_fifo/fifo_section\[0\].impl_bram_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop\[0\].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_0\[6\]) which is driven by a register (e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_output_out\[0\].axis_data_to_chdr_out_out/no_gen_axis_width_conv.gen_async_pyld_fifo.pyld_fifo/fifo_section\[0\].impl_bram_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg\[6\]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: \[DRC REQP-1839\] RAMB36 async control check: The RAMB36E1 e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_output_out\[0\].axis_data_to_chdr_out_out/no_gen_axis_width_conv.gen_async_pyld_fifo.pyld_fifo/fifo_section\[0\].impl_bram_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop\[0\].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram has an input control pin e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_output_out\[0\].axis_data_to_chdr_out_out/no_gen_axis_width_conv.gen_async_pyld_fifo.pyld_fifo/fifo_section\[0\].impl_bram_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop\[0\].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram/ADDRARDADDR\[13\] (net: e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_output_out\[0\].axis_data_to_chdr_out_out/no_gen_axis_width_conv.gen_async_pyld_fifo.pyld_fifo/fifo_section\[0\].impl_bram_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop\[0\].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_0\[7\]) which is driven by a register (e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_output_out\[0\].axis_data_to_chdr_out_out/no_gen_axis_width_conv.gen_async_pyld_fifo.pyld_fifo/fifo_section\[0\].impl_bram_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg\[7\]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: \[DRC REQP-1839\] RAMB36 async control check: The RAMB36E1 e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_output_out\[0\].axis_data_to_chdr_out_out/no_gen_axis_width_conv.gen_async_pyld_fifo.pyld_fifo/fifo_section\[0\].impl_bram_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop\[0\].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram has an input control pin e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_output_out\[0\].axis_data_to_chdr_out_out/no_gen_axis_width_conv.gen_async_pyld_fifo.pyld_fifo/fifo_section\[0\].impl_bram_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop\[0\].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram/ADDRARDADDR\[14\] (net: e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_output_out\[0\].axis_data_to_chdr_out_out/no_gen_axis_width_conv.gen_async_pyld_fifo.pyld_fifo/fifo_section\[0\].impl_bram_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop\[0\].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_0\[8\]) which is driven by a register (e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_output_out\[0\].axis_data_to_chdr_out_out/no_gen_axis_width_conv.gen_async_pyld_fifo.pyld_fifo/fifo_section\[0\].impl_bram_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg\[8\]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: \[DRC REQP-1839\] RAMB36 async control check: The RAMB36E1 e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_output_out\[0\].axis_data_to_chdr_out_out/no_gen_axis_width_conv.gen_async_pyld_fifo.pyld_fifo/fifo_section\[0\].impl_bram_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop\[0\].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram has an input control pin e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_output_out\[0\].axis_data_to_chdr_out_out/no_gen_axis_width_conv.gen_async_pyld_fifo.pyld_fifo/fifo_section\[0\].impl_bram_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop\[0\].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram/ADDRARDADDR\[9\] (net: e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_output_out\[0\].axis_data_to_chdr_out_out/no_gen_axis_width_conv.gen_async_pyld_fifo.pyld_fifo/fifo_section\[0\].impl_bram_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop\[0\].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM36_NO_ECC.ram_0\[3\]) which is driven by a register (e31x_core_inst/rfnoc_image_core_i/b_replay0_1/noc_shell_replay_i/gen_output_out\[0\].axis_data_to_chdr_out_out/no_gen_axis_width_conv.gen_async_pyld_fifo.pyld_fifo/fifo_section\[0\].impl_bram_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg\[3\]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: \[DRC REQP-1840\] RAMB18 async control check: The RAMB18E1 e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/ctrlport_endpoint_i/gen_ctrl_slave.slv_fifo_i/fifo_bram/ram/impl/ram_reg has an input control pin e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/ctrlport_endpoint_i/gen_ctrl_slave.slv_fifo_i/fifo_bram/ram/impl/ram_reg/ENBWREN (net: e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/ctrlport_endpoint_i/gen_ctrl_slave.slv_fifo_i/fifo_bram/ram/impl/p_0_in7_out) which is driven by a register (e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/ctrlport_endpoint_i/gen_async_fifos.in_fifo_i/fifo_section\[0\].impl_srl_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: \[DRC REQP-1840\] RAMB18 async control check: The RAMB18E1 e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/ctrlport_endpoint_i/gen_ctrl_slave.slv_fifo_i/fifo_bram/ram/impl/ram_reg has an input control pin e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/ctrlport_endpoint_i/gen_ctrl_slave.slv_fifo_i/fifo_bram/ram/impl/ram_reg/WEBWE\[0\] (net: e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/ctrlport_endpoint_i/gen_ctrl_slave.slv_fifo_i/fifo_bram/ram/impl/p_0_in7_out) which is driven by a register (e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/ctrlport_endpoint_i/gen_async_fifos.in_fifo_i/fifo_section\[0\].impl_srl_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: \[DRC REQP-1840\] RAMB18 async control check: The RAMB18E1 e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/ctrlport_endpoint_i/gen_ctrl_slave.slv_fifo_i/fifo_bram/ram/impl/ram_reg has an input control pin e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/ctrlport_endpoint_i/gen_ctrl_slave.slv_fifo_i/fifo_bram/ram/impl/ram_reg/WEBWE\[1\] (net: e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/ctrlport_endpoint_i/gen_ctrl_slave.slv_fifo_i/fifo_bram/ram/impl/p_0_in7_out) which is driven by a register (e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/ctrlport_endpoint_i/gen_async_fifos.in_fifo_i/fifo_section\[0\].impl_srl_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: \[DRC REQP-1840\] RAMB18 async control check: The RAMB18E1 e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/ctrlport_endpoint_i/gen_ctrl_slave.slv_fifo_i/fifo_bram/ram/impl/ram_reg has an input control pin e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/ctrlport_endpoint_i/gen_ctrl_slave.slv_fifo_i/fifo_bram/ram/impl/ram_reg/WEBWE\[2\] (net: e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/ctrlport_endpoint_i/gen_ctrl_slave.slv_fifo_i/fifo_bram/ram/impl/p_0_in7_out) which is driven by a register (e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/ctrlport_endpoint_i/gen_async_fifos.in_fifo_i/fifo_section\[0\].impl_srl_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: \[DRC REQP-1840\] RAMB18 async control check: The RAMB18E1 e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/ctrlport_endpoint_i/gen_ctrl_slave.slv_fifo_i/fifo_bram/ram/impl/ram_reg has an input control pin e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/ctrlport_endpoint_i/gen_ctrl_slave.slv_fifo_i/fifo_bram/ram/impl/ram_reg/WEBWE\[3\] (net: e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/ctrlport_endpoint_i/gen_ctrl_slave.slv_fifo_i/fifo_bram/ram/impl/p_0_in7_out) which is driven by a register (e31x_core_inst/rfnoc_image_core_i/b_radio0_0/noc_shell_radio_i/ctrlport_endpoint_i/gen_async_fifos.in_fifo_i/fifo_section\[0\].impl_srl_i/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. \[00:10:15\] Starting Placer Task \[00:10:15\] Current task: Placer +++ Current Phase: Starting \[00:10:15\] Current task: Placer +++ Current Phase: 1 Placer Initialization \[00:10:15\] Current task: Placer +++ Current Phase: 1.1 Placer Initialization Netlist Sorting WARNING: \[Place 30-87\] Partially locked IO Bus is found. Following components of the IO Bus DB_EXP_1_8V are not locked: 'DB_EXP_1_8V\[30\]' 'DB_EXP_1_8V\[29\]' 'DB_EXP_1_8V\[28\]' 'DB_EXP_1_8V\[27\]' 'DB_EXP_1_8V\[26\]' 'DB_EXP_1_8V\[25\]' 'DB_EXP_1_8V\[23\]' 'DB_EXP_1_8V\[22\]' 'DB_EXP_1_8V\[21\]' 'DB_EXP_1_8V\[20\]' 'DB_EXP_1_8V\[19\]' 'DB_EXP_1_8V\[18\]' 'DB_EXP_1_8V\[17\]' 'DB_EXP_1_8V\[16\]' 'DB_EXP_1_8V\[15\]' 'DB_EXP_1_8V\[14\]' 'DB_EXP_1_8V\[13\]' 'DB_EXP_1_8V\[12\]' 'DB_EXP_1_8V\[7\]' 'DB_EXP_1_8V\[4\]' 'DB_EXP_1_8V\[3\]' 'DB_EXP_1_8V\[2\]' 'DB_EXP_1_8V\[1\]' 'DB_EXP_1_8V\[0\]' CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[0\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[10\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[11\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[12\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[13\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[14\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[15\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[16\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[17\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[18\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[19\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[1\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[20\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[21\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[22\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[23\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[24\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[25\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[26\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[27\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[28\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[29\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[2\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[30\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[31\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[3\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[4\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[5\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[6\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[7\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[8\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_in_iob_reg\[9\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[0\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[16\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[17\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[18\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[19\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[1\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[20\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[21\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[22\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[23\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[24\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[25\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[26\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[27\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[28\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[29\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[2\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[30\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[0\].gpio_atr_db_inst/gpio_out_iob_reg\[31\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[0\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[10\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[11\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[12\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[13\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[14\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[15\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[16\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[17\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[18\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[19\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[1\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[20\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[21\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[22\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[23\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[24\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[25\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[26\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[27\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[28\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[29\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[2\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[30\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[31\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[3\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[4\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[5\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[6\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[7\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[8\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_in_iob_reg\[9\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_out_iob_reg\[0\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_out_iob_reg\[16\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_out_iob_reg\[17\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_out_iob_reg\[18\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_out_iob_reg\[19\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_out_iob_reg\[1\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_out_iob_reg\[20\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_out_iob_reg\[21\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_out_iob_reg\[22\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_out_iob_reg\[23\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_out_iob_reg\[24\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_out_iob_reg\[25\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_out_iob_reg\[26\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_out_iob_reg\[27\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_out_iob_reg\[28\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_out_iob_reg\[29\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. CRITICAL WARNING: \[Place 30-73\] Invalid constraint on register 'genblk2\[1\].gpio_atr_db_inst/gpio_out_iob_reg\[2\]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element. WARNING: \[Place 30-568\] A LUT 'e31x_core_inst/tpps_i_2' is driving clock pin of 25 registers. This could lead to large hold time violations. First few involved registers are: WARNING: \[Place 30-172\] Sub-optimal placement for a clock-capable IO pin and PLL pair. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint is set to FALSE allowing your design to continue. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. \[00:10:22\] Current task: Placer +++ Current Phase: 1.2 IO Placement/ Clock Placement/ Build Placer Device WARNING: \[Place 30-770\] High register utilization is forcing place_design to place up to 8 registers per slice which may impact placement success and/or routing congestion. \[00:10:43\] Current task: Placer +++ Current Phase: 1.3 Build Placer Netlist Model \[00:10:44\] Current task: Placer +++ Current Phase: 1.4 Constrain Clocks/Macros \[00:10:44\] Current task: Placer +++ Current Phase: 2 Global Placement \[00:10:49\] Current task: Placer +++ Current Phase: 2.1 Floorplanning \[00:10:55\] Current task: Placer +++ Current Phase: 2.2 Update Timing before SLR Path Opt \[00:11:42\] Current task: Placer +++ Current Phase: 2.4 Global Placement Core \[00:12:05\] Current task: Placer +++ Current Phase: 2.4.1 Physical Synthesis In Placer \[00:12:05\] Current task: Placer +++ Current Phase: 3 Detail Placement \[00:12:20\] Current task: Placer +++ Current Phase: 3.1 Commit Multi Column Macros \[00:12:21\] Current task: Placer +++ Current Phase: 3.3 Area Swap Optimization \[00:12:21\] Current task: Placer +++ Current Phase: 3.4 Pipeline Register Optimization \[00:12:29\] Current task: Placer +++ Current Phase: 3.5 Fast Optimization ERROR: \[Place 30-487\] The packing of instances into the device could not be obeyed. There are a total of 13300 slices in the device, of which 9737 slices are available, however, the unplaced instances require 10808 slices. Please analyze your design to determine if the number of LUTs, FFs, and/or control sets can be reduced. ERROR: \[Place 30-99\] Placer failed with error: 'Detail Placement failed please check previous errors for details.' ERROR: \[Common 17-69\] Command failed: Placer could not place all instances \[00:12:59\] Current task: Placer +++ Current Phase: 3.6 Small Shape Detail Placement \[00:12:59\] Current task: Placer +++ Current Phase: Finished \[00:12:59\] Process terminated. Status: Failure ======================================================== Warnings: 877 Critical Warnings: 122 Errors: 3 make\[1\]: \*\*\* \[Makefile.e31x.inc:121: bin\] Error 1 make\[1\]: Leaving directory '/home/grcusrp/uhd/fpga/usrp3/top/e31x' make: \*\*\* \[Makefile:80: E310_SG3\] Error 2