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View all threadstrying to run make.py rfnoc command
I was trying to get the make.py command to work today, but am having
issues. Here is the command I ran:
./make.py fifo fifo fft -I ~/pybombs/src/rfnoc-LTEblocks/rfnoc/fpga-src/
-d x310 -t X310_RFNOC_HG -m 5 --fill-with-fifos
and here are the errors reported:
INFO: [Synth 8-256] done synthesizing module 'bus_clk_gen' (2#1)
[/home/jmat/pybombs/src/uhd-fpga/usrp3_rfnoc/top/x300/build-X310_RFNOC_HG/.Xil/Vivado-19897-wk-jmat-01/realtime/bus_clk_gen_stub.v:6]
ERROR: [Synth 8-448] named port connection 'CLK_OUT3' does not exist for
instance 'bus_clk_gen' of module 'bus_clk_gen'
[/home/jmat/pybombs/src/uhd-fpga/usrp3_rfnoc/top/x300/x300.v:281]
INFO: [Synth 8-638] synthesizing module 'BUFG'
[/opt/Xilinx/Vivado/2015.4/scripts/rt/data/unisim_comp.v:607]
ERROR: [Synth 8-285] failed synthesizing module 'BUFG'
[/opt/Xilinx/Vivado/2015.4/scripts/rt/data/unisim_comp.v:607]
ERROR: [Synth 8-285] failed synthesizing module 'x300'
[/home/jmat/pybombs/src/uhd-fpga/usrp3_rfnoc/top/x300/x300.v:15]
Finished RTL Elaboration : Time (s): cpu = 00:00:10 ; elapsed = 00:00:16
. Memory (MB): peak = 1147.203 ; gain = 310.871 ; free physical = 9350 ;
free virtual = 29091
RTL Elaboration failed
INFO: [Common 17-83] Releasing license: Synthesis
10 Infos, 28 Warnings, 0 Critical Warnings and 4 Errors encountered.
synth_design failed
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the
console or run log file for details
INFO: [Common 17-206] Exiting Vivado at Wed Sep 7 12:20:46 2016...
make[1]: *** [bin] Error 1
make[1]: Leaving directory
`/home/jmat/pybombs/src/uhd-fpga/usrp3_rfnoc/top/x300'
make: *** [X310_RFNOC_HG] Error 2
Hello Jason,
I just ran the same command to see what is happening and the build is still
running. However, I believe I am passed that step where you get the error.
Could you please retry running the command after running a
$ make cleanall
at the top/x300/ directory? If you still get problems, could you please
send us a more extended output?
This may not be an issue related with the make.py per se, but there is some
things to keep in mind:
-
the script was recently updated to make the -I directive optional.
Although it was first intended to be used with OOT modules, it was rather
clear that this eases the fpga build even for provided blocks. That means
that you don't have to point to your OOT module path if you are not
directly using an OOT module. -
The name of the blocks that you provide to the script are the, lets say,
suffixes of the fpga-given names. I.e. if the block that you want to add is
the "noc_block_axi_fifo_loopback", you run:$ make.py axi_fifo_loopback {etc}....
As there is no "noc_block_fifo", by running
$ make.py fifo {etc}...
you'll run into issues as that block doesn't exist in the Ettus-provided
blocks (NOTE: if you created a noc_block_fifo in your rfnoc-LTEblocks, then
you are doing things right!).
So just to be clear, the reason why this convention was adopted is because,
although noc_block_FOO is indeed the name that you'd be looking for, all
blocks have the same prefix and, given the lack of tab-completion, writing
the the same prefix for all your blocks one per one may result cumbersome
after a while. The documentation will be updated ASAP to make this part
clear. You can check which blocks are available by looking for the
noc_blocks at {fpga_repo}/usrp3_rfnoc/lib/rfnoc/Makefile.srcs. As of now,
the blocks that the make.py will add with this convention are:
- axi_fifo_loopback
- axi_dma_fifo
- fir_filter
- fft
- null_source_sink
- schmidl_cox
- packet_resizer
- split_stream
- vector_iir
- addsub
- window
- keep_one_in_n
- pfb
- export_io
- conv_encoder_qpsk
- siggen
- logpwr
- fosphor
- moving_avg
- ddc
- duc
This list may vary as more blocks are added and depending in which commit
or repo you are. Also every OOT block created with RFNoCmodtool will follow
the same convention.
We know that this stiil requires you to know, for example, the names of the
blocks listed above. But we are working on ways to make the RFNoC custom
builds even more intuitive.
Cheers,
-Nicolas
On Wed, Sep 7, 2016 at 9:27 AM, Jason Matusiak via USRP-users <
usrp-users@lists.ettus.com> wrote:
I was trying to get the make.py command to work today, but am having
issues. Here is the command I ran:
./make.py fifo fifo fft -I ~/pybombs/src/rfnoc-LTEblocks/rfnoc/fpga-src/
-d x310 -t X310_RFNOC_HG -m 5 --fill-with-fifos
and here are the errors reported:
INFO: [Synth 8-256] done synthesizing module 'bus_clk_gen' (2#1)
[/home/jmat/pybombs/src/uhd-fpga/usrp3_rfnoc/top/x300/build-
X310_RFNOC_HG/.Xil/Vivado-19897-wk-jmat-01/realtime/bus_clk_gen_stub.v:6]
ERROR: [Synth 8-448] named port connection 'CLK_OUT3' does not exist for
instance 'bus_clk_gen' of module 'bus_clk_gen'
[/home/jmat/pybombs/src/uhd-fpga/usrp3_rfnoc/top/x300/x300.v:281]
INFO: [Synth 8-638] synthesizing module 'BUFG'
[/opt/Xilinx/Vivado/2015.4/scripts/rt/data/unisim_comp.v:607]
ERROR: [Synth 8-285] failed synthesizing module 'BUFG'
[/opt/Xilinx/Vivado/2015.4/scripts/rt/data/unisim_comp.v:607]
ERROR: [Synth 8-285] failed synthesizing module 'x300'
[/home/jmat/pybombs/src/uhd-fpga/usrp3_rfnoc/top/x300/x300.v:15]
Finished RTL Elaboration : Time (s): cpu = 00:00:10 ; elapsed = 00:00:16 .
Memory (MB): peak = 1147.203 ; gain = 310.871 ; free physical = 9350 ; free
virtual = 29091
RTL Elaboration failed
INFO: [Common 17-83] Releasing license: Synthesis
10 Infos, 28 Warnings, 0 Critical Warnings and 4 Errors encountered.
synth_design failed
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the
console or run log file for details
INFO: [Common 17-206] Exiting Vivado at Wed Sep 7 12:20:46 2016...
make[1]: *** [bin] Error 1
make[1]: Leaving directory `/home/jmat/pybombs/src/uhd-fp
ga/usrp3_rfnoc/top/x300'
make: *** [X310_RFNOC_HG] Error 2
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Nicolas,
Thank you for the information. I ran a pybombs update (to help with the
include directory issue), did a make cleanall, and am rerunning the
build now.
That is good to know how the naming convention works for the blocks, I
didn't glean that from reading through the example in the KB.
I'll try your tips and report back. Thanks!
On 09/07/2016 01:57 PM, Nicolas Cuervo wrote:
Hello Jason,
I just ran the same command to see what is happening and the build is
still running. However, I believe I am passed that step where you get
the error. Could you please retry running the command after running a
$ make cleanall
at the top/x300/ directory? If you still get problems, could you
please send us a more extended output?
This may not be an issue related with the make.py per se, but there is
some things to keep in mind:
-
the script was recently updated to make the -I directive optional.
Although it was first intended to be used with OOT modules, it was
rather clear that this eases the fpga build even for provided blocks.
That means that you don't have to point to your OOT module path if you
are not directly using an OOT module. -
The name of the blocks that you provide to the script are the, lets
say, suffixes of the fpga-given names. I.e. if the block that you want
to add is the "noc_block_axi_fifo_loopback", you run:$ make.py axi_fifo_loopback {etc}....
As there is no "noc_block_fifo", by running
$ make.py fifo {etc}...
you'll run into issues as that block doesn't exist in the
Ettus-provided blocks (NOTE: if you created a noc_block_fifo in your
rfnoc-LTEblocks, then you are doing things right!).
So just to be clear, the reason why this convention was adopted is
because, although noc_block_FOO is indeed the name that you'd be
looking for, all blocks have the same prefix and, given the lack of
tab-completion, writing the the same prefix for all your blocks one
per one may result cumbersome after a while. The documentation will be
updated ASAP to make this part clear. You can check which blocks are
available by looking for the noc_blocks at
{fpga_repo}/usrp3_rfnoc/lib/rfnoc/Makefile.srcs. As of now, the blocks
that the make.py will add with this convention are:
- axi_fifo_loopback
- axi_dma_fifo
- fir_filter
- fft
- null_source_sink
- schmidl_cox
- packet_resizer
- split_stream
- vector_iir
- addsub
- window
- keep_one_in_n
- pfb
- export_io
- conv_encoder_qpsk
- siggen
- logpwr
- fosphor
- moving_avg
- ddc
- duc
This list may vary as more blocks are added and depending in which
commit or repo you are. Also every OOT block created with RFNoCmodtool
will follow the same convention.
We know that this stiil requires you to know, for example, the names
of the blocks listed above. But we are working on ways to make the
RFNoC custom builds even more intuitive.
Cheers,
-Nicolas
On Wed, Sep 7, 2016 at 9:27 AM, Jason Matusiak via USRP-users
<usrp-users@lists.ettus.com mailto:usrp-users@lists.ettus.com> wrote:
I was trying to get the make.py command to work today, but am
having issues. Here is the command I ran:
./make.py fifo fifo fft -I
~/pybombs/src/rfnoc-LTEblocks/rfnoc/fpga-src/ -d x310 -t
X310_RFNOC_HG -m 5 --fill-with-fifos
and here are the errors reported:
INFO: [Synth 8-256] done synthesizing module 'bus_clk_gen' (2#1)
[/home/jmat/pybombs/src/uhd-fpga/usrp3_rfnoc/top/x300/build-X310_RFNOC_HG/.Xil/Vivado-19897-wk-jmat-01/realtime/bus_clk_gen_stub.v:6]
ERROR: [Synth 8-448] named port connection 'CLK_OUT3' does not
exist for instance 'bus_clk_gen' of module 'bus_clk_gen'
[/home/jmat/pybombs/src/uhd-fpga/usrp3_rfnoc/top/x300/x300.v:281]
INFO: [Synth 8-638] synthesizing module 'BUFG'
[/opt/Xilinx/Vivado/2015.4/scripts/rt/data/unisim_comp.v:607]
ERROR: [Synth 8-285] failed synthesizing module 'BUFG'
[/opt/Xilinx/Vivado/2015.4/scripts/rt/data/unisim_comp.v:607]
ERROR: [Synth 8-285] failed synthesizing module 'x300'
[/home/jmat/pybombs/src/uhd-fpga/usrp3_rfnoc/top/x300/x300.v:15]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:10 ; elapsed =
00:00:16 . Memory (MB): peak = 1147.203 ; gain = 310.871 ; free
physical = 9350 ; free virtual = 29091
---------------------------------------------------------------------------------
RTL Elaboration failed
INFO: [Common 17-83] Releasing license: Synthesis
10 Infos, 28 Warnings, 0 Critical Warnings and 4 Errors encountered.
synth_design failed
ERROR: [Common 17-69] Command failed: Synthesis failed - please
see the console or run log file for details
INFO: [Common 17-206] Exiting Vivado at Wed Sep 7 12:20:46 2016...
make[1]: *** [bin] Error 1
make[1]: Leaving directory
`/home/jmat/pybombs/src/uhd-fpga/usrp3_rfnoc/top/x300'
make: *** [X310_RFNOC_HG] Error 2
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