On Wed, October 26, 2022 1:14 pm, Thomas Tammann via time-nuts wrote:

Don't forget that 10MHz is not a frequency related to any integer multiple
of common sampling frequencies, so you will also want to check the phase
noise of whatever mechanism you are using to convert to e.g. 11.2896MHz or
12.2880MHz

--
Chris Caudle

Hi

Just to add a bit to this ….

The most common way (these days) to get from 10 MHz to “something else” is with a PLL.
That PLL will be designed with a noise bandwidth. It is not unusual to see a bandwidth
somewhere in the 10 Hz to 1 KHz range if the PLL is running a crystal oscillator to generate
the output. The better that oscillator is, the smaller the bandwidth that likely will be used.

Once you are outside that bandwidth, the phase noise of the reference oscillator does not
really matter. All of the noise is coming from the output oscillator.

Why does this matter?

Reference devices can have very good close in phase noise, but not so great noise far
removed from carrier. If you have a PLL at 10 Hz, that’s probably not a big deal. If your
PLL is set up for something a bit crazy ( maybe in the KHz range ….) it can matter quite
a bit.

Yes, there’s a lot more to it than this. Noise floors on various parts of the system come
into play. Spur generation can be a bigger problem in some systems than broadband
noise. The allowable operating point ( = comparison frequency ) for the phase detector
will most certainly get into the mix on many designs.

Once you move past phase noise and over to ADEV, there are equally bothersome
questions. Things like temperature stability of the device ( and of your operating environment)
will come into play. ADEV will give you one set of numbers other “DEV”’s will paint
a different picture. This or that application may be better described by this or that DEV.
There are a lot of papers out there talking about custom DEV’s to better suit this or that
system’s performance requirements.

So, as noted previously, it’s  best to do a bit of a deep dive into “what’s next” before
you start picking and sorting out multiple reference oscillators. It is very easy to get
hung up on numbers that, in the end, turn out not to matter very much.

Bob

Hi,

Further, what is the critical for the application at hand. For audio I
strongly recommend looking at the work of Julian Dunn that connected
phase-noise with side-band generation and sensitivity for the hearing to
that, producing phase noise requirements on reference clock to address
it, and from this you can go back to your oscillator and synthesis to
see how the requirements is being met.

Julian Dunn published a number of papers on jitter on AES/EBU signal in
AES but also through sources such as Audio Precision.

With that knowledge at hand, I'm sure we can provide the guidance on
synthesis to achieve it.

Cheers,
Magnus

On 2022-10-27 14:49, Bob kb8tq via time-nuts wrote:

Very cool, thanks so much Bob

As much as I understand your answer ;-) it makes all sense.

The challenge is really, that making my own clock to attach to my switch is way out of my league. Hence, I buy what I can and I try to understand the quality of the piece I bought.

Lets say there are two “identical” clocks, all I care really is the end result and how they compare to each other. And, as much as I understand, the phase noise is a good indicator.

I bough this clock on ALibaba with the promise that phase noise at 1HZ is 114dB…and I want to verify ;-)

Again, I appreciate very much how this community helps a noob ;-)

Cheers
Tom W5TAQ

Hi

Having measured a number of similar ( = same part number ) OCXO’s….
It’s a pretty good bet that the phase noise is in the -110 to -115 range at
1 Hz offset.

Without the “deep dive” into this or that, there is no real way of knowing
what impact a 1 Hz phase noise or 10 second ADEV (or any) number will have.
It could be several orders of magnitude better than something else in the
system.

As you divide frequency, the phase noise gets better. It should improve by
20 log N where N is the divider. Divide 10 MHz to 1 MHz with a chip and
phase noise gets 20 db better. Your -114 number is now -134. In an ideal
world with perfect parts, it would just keep getting better the more you divide.

The world is never that simple.  Chips are never noiseless. They always have
noise floors on the output stages and various other noise sources. Once you
hit this or that limit, the chip is what you worry about and not the reference source.
In a PLL, this can pop up pretty fast.

While we talk about ADEV ( or any DEV ) and phase noise being independent
measures, they really aren’t. Back in the day, gear that measured phase
noise typically became impractical below 1 Hz ( = it took a very long time
to get data). Folks switched over to an ADEV measure mainly because the
process was more practical. These days, an ADEV at 0.001 seconds is doable.
If you have enough time, phase noise at 0.01 Hz can be done ( = it still takes
a long time ….).  Oddly enough, while phase noise improves by 20 log N when
you divide, ADEV does not change.

As Magnus points out, you may be able to start at the “far end” of the system
and come up with estimates of what might matter.  It’s always better to spend
hard earned cash on whatever the weak link is :)

Bob

On Thu, 27 Oct 2022 10:46:03 -0400
Bob kb8tq via time-nuts time-nuts@lists.febo.com wrote:

Small nitpick:

The 20log(N) formula[1] is only valid if aliasing of noise can be prevented.
I.e. if one uses a digital divider (e.g. a bunch of D-flipflops) then the
aliasing will increase the relative noise and the noise scaling is reduced
to 10log(N).

To achieve the 20*log(N) one needs a divider that generates a sinusoid
like a DDS or at the very least a trapezoid/triangular waveform like
a Λ-divider[2] in order to get the harmonics of the impulse sensitivity
function[3,4] to decay quickly with increasing frequency/harmonic number.

		Attila Kinali

[1] With log() being the logarithm of base 10. And result in dB

[2] "The Sampling Theorem in Pi and Lambda Digital Frequency Dividers",
by Claudio Calosso and Enrico Rubiola, 2013
http://rubiola.org/pdf-articles/conference/2013-ifcs-Frequency-dividers.pdf

[3] "A General Theory of Phase Noise in Electrical Oscillators",
by Hajimiri and Lee, 1998
https://doi.org/10.1109/4.658619
Note: Do not use the formulas in this paper for oscillators. The theory is flawed
and does not apply for systems with a feedback loop, like oscillators. Use [5] instead.

[4] "A Physical Sine-to-Square Converter Noise Model",
by yours truly, 2018
https://people.mpi-inf.mpg.de/~adogan/pubs/IFCS2018_comparator_noise.pdf

[5] "Phase noise in oscillators: a unifying theory and numerical methods
for characterization", by Alper Demir, Amit Mehrotra, and Jaijeet Roychowdhury, 2000
https://doi.org/10.1109/81.847872

In science if you know what you are doing you should not be doing it.
In engineering if you do not know what you are doing you should not be doing it.
-- Richard W. Hamming, The Art of Doing Science and Engineering