Hi

Yes, this is picky, but there’s a point to it. The CVHD-950 is a VCXO and not
a TCXO. TCXO implies it has some level of temperature compensation. VCXO
simply says there’s a crystal in it. At the price point, it’s a good bet it’s uncompensated.
That means you will see some pretty significant temperature / draft sort of effects
on the output.

VCXO’s typically have fairly low loop Q and thus are not going to win many races
in the “who’s best at ADEV” category. Of all the crystal oscillator categories they
will lag behind in this category. Just how far behind depends on a bunch of things.
Swing range is one of the many.

Best guess ADEV at one second …. 1x10^-9 to 1x10^-8 in a stable environment.
Open the lab window while you are running the test and who knows. (Yes, I’ve
actually run into folks who have done that while running ADEV …..).

Testing wise, a single mixer setup running against a 100 MHz OCXO would be
a cheap and quick way to go.

Bob

Am 2023-03-24 22:00, schrieb Christophe Huygens via time-nuts:

I've made a takeout from my 432 MHz -> 32 MHz transverter published in
DUBUS 2 or 3
2022. It is just the ECS 100 MHz xtal oven, PLL to lock it to 10 MHz and
further
multiplier to 300 or 400 MHz. My GPS delivers 10 MHz. I simply take the
interesting
LVCMOS harmonic and dump it into a SAW or LC filter. There seem to be no
SAWs for 300 MHz.

<
https://www.digikey.de/de/products/filter/oszillatoren/172?s=N4IgTCBcDaIKYGMDOACRB7BKwFYwQF0BfIA

The 10->100 MHz PLL is 4046 + 74LVC161 1/10 divider. The 9046 is not
available.
With a low enough filter corner, PN depends on the XO only.
I asked ECS for the phase noise plots of their 100 MHz oven and got them
with
no NDA attached, so here it is. I think the layout can accommodate the
CVHD-950
but this has never been tested. The entire takeout has not yet seen
solder.

300 MHz is a more lucky choice WRT amplitude than 400. The oven already
delivers
LVCMOS so there is not much to be lost by further buffering. 300/400 MHz
happen to
be the fastest clock frequencies for the LMX2594 synthesizer in
fractional/integer
mode.

My LVC161 prescaler created some spurs at frequencies one would never
expect.
That's why it has it's own small house now.
I'm building stereo downconverters for my Timepod @100 MHz and X-band,
but
day-time work takes precedence and my VNA is ill.
A few empty boards, Gerbers or Altium Designer files are available.
Outside EU, Gerber files for JLCPCB will be less ado than a leftover
board.

regards,
Gerhard  DK4XP

It’s always an option to invert the loop and discipline a higher frequency oscillator driving a synthesizer to produce a 10mhz output and compare the 10mhz output with the 10mhz reference phase. Potentially, the relatively low frequency of 10MHz and signals already being in the right ballpark as far as amplitude could cut the component count while having a low noise floor.

A 133.333mhz VCXO with a relatively strong third harmonic might be a most direct route to 400 MHz without two doublers or boosting the weaker even harmonic, while a nice even 100MHz vcxo would be great for 300MHz.

The ultimate in clean might be a GPS disciplined rubidium, for the 10 MHz source as many gps 10mhz outputs aren’t all that low phase noise (if the jitter is say 7ns versus 70fs, it’s probably reasonable to say without too much qualification).

Get Outlook for iOShttps://aka.ms/o0ukef

From: Gerhard Hoffmann via time-nuts time-nuts@lists.febo.com
Sent: Saturday, March 25, 2023 12:10:56 PM
To: Discussion of precise time and frequency measurement time-nuts@lists.febo.com
Cc: ghf@hoffmann-hochfrequenz.de ghf@hoffmann-hochfrequenz.de
Subject: [time-nuts] Re: Characterizing a 100M TCXO

Am 2023-03-24 22:00, schrieb Christophe Huygens via time-nuts:

I've made a takeout from my 432 MHz -> 32 MHz transverter published in
DUBUS 2 or 3
2022. It is just the ECS 100 MHz xtal oven, PLL to lock it to 10 MHz and
further
multiplier to 300 or 400 MHz. My GPS delivers 10 MHz. I simply take the
interesting
LVCMOS harmonic and dump it into a SAW or LC filter. There seem to be no
SAWs for 300 MHz.

<
https://www.digikey.de/de/products/filter/oszillatoren/172?s=N4IgTCBcDaIKYGMDOACRB7BKwFYwQF0BfIA

The 10->100 MHz PLL is 4046 + 74LVC161 1/10 divider. The 9046 is not
available.
With a low enough filter corner, PN depends on the XO only.
I asked ECS for the phase noise plots of their 100 MHz oven and got them
with
no NDA attached, so here it is. I think the layout can accommodate the
CVHD-950
but this has never been tested. The entire takeout has not yet seen
solder.

300 MHz is a more lucky choice WRT amplitude than 400. The oven already
delivers
LVCMOS so there is not much to be lost by further buffering. 300/400 MHz
happen to
be the fastest clock frequencies for the LMX2594 synthesizer in
fractional/integer
mode.

My LVC161 prescaler created some spurs at frequencies one would never
expect.
That's why it has it's own small house now.
I'm building stereo downconverters for my Timepod @100 MHz and X-band,
but
day-time work takes precedence and my VNA is ill.
A few empty boards, Gerbers or Altium Designer files are available.
Outside EU, Gerber files for JLCPCB will be less ado than a leftover
board.

regards,
Gerhard  DK4XP

I was curious about the phase noise numbers and I started plugging them
into spreadsheets and online calculators.  I cannot seem to get matching
numbers for integrated jitter.  For oscillator 2, the jpg indicates
about 66fS on the HP5052.  I took this as the reference.  The SI Time
https://www.sitime.com/phase-noise-and-jitter-calculator online tool
was admittedly close at 59 fS.  The Marki
https://rf-tools.com/jitter/tool gave 88fS.  My spreadsheet, which
calculates area with the trapezoidal rule is 76 fS.  I calculated
another way, by finding the segment jitter in dBc, converting to
radians, squaring, summing, etc and get about 72 fS.

I am not a mathematician, but this seems simple.  Is there some subtlety
I am overlooking?  Or should we not be concerned about a few fS?!

On 2023-03-25 1:10 PM, Gerhard Hoffmann via time-nuts wrote:

--
Jim

What was your lower frequency limit in the integral for the total
phase noise power (assuming the upper limit was that of the last point
given on the datasheet of 1MHz)?

It makes quite a big difference to the total integrated noise power
and hence to the computed RMS jitter and also the maximum error in the
trapezoid rule will occur at the low frequency tail.

Alan
On Fri, 31 Mar 2023 at 02:26, Jim Muehlberg via time-nuts
time-nuts@lists.febo.com wrote:

Hi

Which limit is the “gotcha” depends very much on the phase noise of the source and
the range you are looking at.

In some cases a small tweak at the low end makes a big impact and changing the high
limit does almost nothing. In other cases, changing the low limit has very little impact
and the high limit it what gets you.

Are any of the changes “zero impact”? If you go to enough decimal places, they certainly
will not be. The input data has some limits to it. Believing any jitter number to three or four
significant figures … hmmm ….

Bob