That's what I want to know. What lines do you comment out, in which files? Is it in Ettus FPGA code or is it a part of Ettus firmware code?

Also, if you want to modify the data received by the SDR RX port, how do you do that without facing the loopback error?

--
Thanks and Regards
Shoor

On Sep 26, 2017 11:18 AM, Ezequiel Alfíe ealfie@gmail.com wrote:
Hi,

I ran into that issue once and I simply recompiled UHD with the relevant lines commented out.

regards

On Mon, Sep 25, 2017 at 3:54 PM, Shoorveer Singh via USRP-users <usrp-users@lists.ettus.commailto:usrp-users@lists.ettus.com> wrote:
Hi all,

I am using USRP B200mini/B205 to develop a custom DSP. For that purpose, I am trying to find an insertion point in the Ettus FPGA code.
I started with modifying the code in b205.v by tying RX and TX to a constant value and expecting to see the same value when running SDR. The code compiles and I am able to generate the FPGA bit file, but when I try to run SDR, I get the following error:

Detected Device: B200mini
-- Loading FPGA image: /usr/local/share/uhd/images/usrp_b200mini_fpga.bin... done
-- Operating over USB 3.
-- Initialize CODEC control...
-- Initialize Radio control...
-- Performing register loopback test... pass
-- Performing CODEC loopback test... fail
Traceback (most recent call last):
File "/home/nev/AuesLayer1Stuff/importantGRC/top_block.py", line 292, in <module>
main()
File "/home/nev/AuesLayer1Stuff/importantGRC/top_block.py", line 286, in main
tb = top_block_cls()
File "/home/nev/AuesLayer1Stuff/importantGRC/top_block.py", line 199, in init
channels=range(1),
File "/usr/local/lib/python2.7/dist-packages/gnuradio/uhd/init.py", line 122, in constructor_interceptor
return old_constructor(*args)
File "/usr/local/lib/python2.7/dist-packages/gnuradio/uhd/uhd_swig.py", line 2681, in make
return _uhd_swig.usrp_source_make(*args)
RuntimeError: RuntimeError: CODEC loopback test failed.

How can I bypass this error? And where should I look in the Ettus FPGA code if I want to modify captured data.

--
Thanks and Regards
Shoor

USRP-users mailing list
USRP-users@lists.ettus.commailto:USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com

Hey Shoor,

This test is in the USRP drivers, see “ad936x_manager.cpp”

https://github.com/EttusResearch/uhd/blob/7ac01c7f979aab8fac5e62f596ff0af52cedec40/host/lib/usrp/common/ad936x_manager.cpp

If you wanted, you could comment out the if statement that throws an error on line 131.  Or you could remove the entire loop that runs the test.

The test assumes there is a path from host through FPGA to AD9364 and back to the host, sounds like you severed that path, so the test words never make it there and back.

-Trip

From: USRP-users [mailto:usrp-users-bounces@lists.ettus.com] On Behalf Of Shoorveer Singh via USRP-users
Sent: Tuesday, September 26, 2017 2:23 PM
To: Ezequiel Alfíe ealfie@gmail.com
Cc: Josh Sendall via USRP-users usrp-users@lists.ettus.com
Subject: Re: [USRP-users] Inserting custom DSP code in B200mini, CODEC loopback test failing

That's what I want to know. What lines do you comment out, in which files? Is it in Ettus FPGA code or is it a part of Ettus firmware code?

Also, if you want to modify the data received by the SDR RX port, how do you do that without facing the loopback error?

--
Thanks and Regards
Shoor

On Sep 26, 2017 11:18 AM, Ezequiel Alfíe <ealfie@gmail.commailto:ealfie@gmail.com> wrote:
Hi,

I ran into that issue once and I simply recompiled UHD with the relevant lines commented out.

regards

On Mon, Sep 25, 2017 at 3:54 PM, Shoorveer Singh via USRP-users <usrp-users@lists.ettus.commailto:usrp-users@lists.ettus.com> wrote:
Hi all,

I am using USRP B200mini/B205 to develop a custom DSP. For that purpose, I am trying to find an insertion point in the Ettus FPGA code.
I started with modifying the code in b205.v by tying RX and TX to a constant value and expecting to see the same value when running SDR. The code compiles and I am able to generate the FPGA bit file, but when I try to run SDR, I get the following error:

Detected Device: B200mini
-- Loading FPGA image: /usr/local/share/uhd/images/usrp_b200mini_fpga.bin... done
-- Operating over USB 3.
-- Initialize CODEC control...
-- Initialize Radio control...
-- Performing register loopback test... pass
-- Performing CODEC loopback test... fail
Traceback (most recent call last):
File "/home/nev/AuesLayer1Stuff/importantGRC/top_block.py", line 292, in <module>
main()
File "/home/nev/AuesLayer1Stuff/importantGRC/top_block.py", line 286, in main
tb = top_block_cls()
File "/home/nev/AuesLayer1Stuff/importantGRC/top_block.py", line 199, in init
channels=range(1),
File "/usr/local/lib/python2.7/dist-packages/gnuradio/uhd/init.py", line 122, in constructor_interceptor
return old_constructor(*args)
File "/usr/local/lib/python2.7/dist-packages/gnuradio/uhd/uhd_swig.py", line 2681, in make
return _uhd_swig.usrp_source_make(*args)
RuntimeError: RuntimeError: CODEC loopback test failed.

How can I bypass this error? And where should I look in the Ettus FPGA code if I want to modify captured data.

--
Thanks and Regards
Shoor

USRP-users mailing list
USRP-users@lists.ettus.commailto:USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com

Hi James,

I did what you suggested and it works! Thanks a ton!

—
Regards
Shoor

From: "Humphries, James R." <humphriesjr@ornl.govmailto:humphriesjr@ornl.gov>
Date: Tuesday, September 26, 2017 at 11:36 AM
To: Shoorveer Singh <Shoorveer.Singh@privoro.commailto:Shoorveer.Singh@privoro.com>, Ezequiel Alfíe <ealfie@gmail.commailto:ealfie@gmail.com>, "usrp-users@lists.ettus.commailto:usrp-users@lists.ettus.com" <usrp-users@lists.ettus.commailto:usrp-users@lists.ettus.com>
Subject: RE: [USRP-users] Inserting custom DSP code in B200mini, CODEC loopback test failing

Hey Shoor,

This test is in the USRP drivers, see “ad936x_manager.cpp”

https://github.com/EttusResearch/uhd/blob/7ac01c7f979aab8fac5e62f596ff0af52cedec40/host/lib/usrp/common/ad936x_manager.cpp

If you wanted, you could comment out the if statement that throws an error on line 131.  Or you could remove the entire loop that runs the test.

The test assumes there is a path from host through FPGA to AD9364 and back to the host, sounds like you severed that path, so the test words never make it there and back.

-Trip

From: USRP-users [mailto:usrp-users-bounces@lists.ettus.com] On Behalf Of Shoorveer Singh via USRP-users
Sent: Tuesday, September 26, 2017 2:23 PM
To: Ezequiel Alfíe <ealfie@gmail.commailto:ealfie@gmail.com>
Cc: Josh Sendall via USRP-users <usrp-users@lists.ettus.commailto:usrp-users@lists.ettus.com>
Subject: Re: [USRP-users] Inserting custom DSP code in B200mini, CODEC loopback test failing

That's what I want to know. What lines do you comment out, in which files? Is it in Ettus FPGA code or is it a part of Ettus firmware code?

Also, if you want to modify the data received by the SDR RX port, how do you do that without facing the loopback error?

--
Thanks and Regards
Shoor

On Sep 26, 2017 11:18 AM, Ezequiel Alfíe <ealfie@gmail.commailto:ealfie@gmail.com> wrote:
Hi,

I ran into that issue once and I simply recompiled UHD with the relevant lines commented out.

regards

On Mon, Sep 25, 2017 at 3:54 PM, Shoorveer Singh via USRP-users <usrp-users@lists.ettus.commailto:usrp-users@lists.ettus.com> wrote:
Hi all,

I am using USRP B200mini/B205 to develop a custom DSP. For that purpose, I am trying to find an insertion point in the Ettus FPGA code.
I started with modifying the code in b205.v by tying RX and TX to a constant value and expecting to see the same value when running SDR. The code compiles and I am able to generate the FPGA bit file, but when I try to run SDR, I get the following error:

Detected Device: B200mini
-- Loading FPGA image: /usr/local/share/uhd/images/usrp_b200mini_fpga.bin... done
-- Operating over USB 3.
-- Initialize CODEC control...
-- Initialize Radio control...
-- Performing register loopback test... pass
-- Performing CODEC loopback test... fail
Traceback (most recent call last):
File "/home/nev/AuesLayer1Stuff/importantGRC/top_block.py", line 292, in <module>
main()
File "/home/nev/AuesLayer1Stuff/importantGRC/top_block.py", line 286, in main
tb = top_block_cls()
File "/home/nev/AuesLayer1Stuff/importantGRC/top_block.py", line 199, in init
channels=range(1),
File "/usr/local/lib/python2.7/dist-packages/gnuradio/uhd/init.py", line 122, in constructor_interceptor
return old_constructor(*args)
File "/usr/local/lib/python2.7/dist-packages/gnuradio/uhd/uhd_swig.py", line 2681, in make
return _uhd_swig.usrp_source_make(*args)
RuntimeError: RuntimeError: CODEC loopback test failed.

How can I bypass this error? And where should I look in the Ettus FPGA code if I want to modify captured data.

--
Thanks and Regards
Shoor

USRP-users mailing list
USRP-users@lists.ettus.commailto:USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com