Normand Martel <martelno@yahoo.com> wrote: > It was part of a Marconi (damn, i don't remember the > model number, but it was an OOOOOLD model), more > precisely the 600 MHz divide by ten prescaler. > > The input divider was based on two tunnel diodes that > acted as a div. by two divider followed by the really > most bizarre divide by five unit i ever saw: Fifteen > discrete NPN transistors arranged in a star (or > pentagon (Helloooo Echelon!! ) ) topology with the > input placed at the center of the star. The 15 > transistor were in a symmetrical loop of 5 three > transistor units working in a closed loop. > > Years later, i've made searches to find the schematic > of this prescaler, but without the model number, this > is quasi-impossible. > > If one of this forum's members has this schematic, i > would be pleased to ask for a copy! I would make a very straightforward guess that the pentagon was simply a divide-by-five ring counter. Each shift register is two transistors... third transistor might be for clock buffering, or maybe (would require a slight break in symmetry) initialization to a known state? Too many people seem to neglect the ring counter and go straight to binary counters. Not sure if this is a defect of the educational materials replicated throughout the decades or what. The ring counter is not a one-trick-pony, instead it solves (AUTOMATICALLY) all the glitches encountered with decoding states from binary counters. Tim.

At 5:31 PM -0400 8/8/06, John Ackermann N8UR wrote: >Randy Warner said the following on 08/08/2006 03:23 PM: > >> I have been seeing a lot of traffic concerning making 10MHz frequency >> dividers using PIC's. While they provide an elegant solution to >> providing an accurate 1PPS from a precision source, I have to ask if >> there is a reason for going this route? I am just using three HCT40103 >> down counters hooked to a DS4000 to get what I think is a very stable >> 1PPS. Am I missing something? I realize 40103's are as old as dirt (I >> guess I am showing my 4000 series CMOS days), but the HCT series have >> plenty of bandwidth. > >Hi Randy -- > >I think the concern in using the older discrete devices is their >potential for jitter in general, and temperature sensitivity on top of >that. But I've never done any experiments on just how big a problem >those issues are. > >John All this talk of frequency dividers brings up a point - there are good ways and bad ways to divide 10 MHz down to 1PPS. The bad way is to just string seven 7490 ripple counters together - the jitter caused by 28 slow flip-flop stages in series is going to be rather big. Adding a resynchronizer to the 1PPS signal made from a fast flip-flop (74FCT74) and clocked by 10 MHz is the way to go. Just make sure that your divider chain doesn't cause enough delay that the resyncer's input sees a transition near the clock's edge! To deal with that, add resynchronizers whenever the propagation delay is approaching the clock period. -- --David Forbes, Tucson, AZ http://www.cathodecorner.com/

Or use 74193 synchronous counters. You will have only one gate per chip worth of jitter. Didier David Forbes wrote: > At 5:31 PM -0400 8/8/06, John Ackermann N8UR wrote: > >> Randy Warner said the following on 08/08/2006 03:23 PM: >> >> >>> I have been seeing a lot of traffic concerning making 10MHz frequency >>> dividers using PIC's. While they provide an elegant solution to >>> providing an accurate 1PPS from a precision source, I have to ask if >>> there is a reason for going this route? I am just using three HCT40103 >>> down counters hooked to a DS4000 to get what I think is a very stable >>> 1PPS. Am I missing something? I realize 40103's are as old as dirt (I >>> guess I am showing my 4000 series CMOS days), but the HCT series have >>> plenty of bandwidth. >>> >> Hi Randy -- >> >> I think the concern in using the older discrete devices is their >> potential for jitter in general, and temperature sensitivity on top of >> that. But I've never done any experiments on just how big a problem >> those issues are. >> >> John >> > > All this talk of frequency dividers brings up a point - there are > good ways and bad ways to divide 10 MHz down to 1PPS. The bad way is > to just string seven 7490 ripple counters together - the jitter > caused by 28 slow flip-flop stages in series is going to be rather > big. > > Adding a resynchronizer to the 1PPS signal made from a fast flip-flop > (74FCT74) and clocked by 10 MHz is the way to go. Just make sure that > your divider chain doesn't cause enough delay that the resyncer's > input sees a transition near the clock's edge! To deal with that, add > resynchronizers whenever the propagation delay is approaching the > clock period. > > > >