Re: [time-nuts] V standards
Hi Bruce,
yup, I thought that circuit and it's claim to 32 bit resolution was over the
top too, I didn't actually read the details.
Coarsedac changes are an issue as you mentioned, but one can get around them
by scaling the two dacs in a way to only use a couple of bits from the
coarsedac, and operate most of the time using just the fine dac.
This is similar to a mechanical coarse adjustment (such as on the 10811A)
setting the approximate voltage range, with the EFC done by the fine dac.
If you use a 16 - 18 bit fine dac, and 6 - 8 bits of a coarse dac then this
works quite well, and with a low aging SC-cut crystal you may never see a
coarsedac change, while still having over 21+ bits of overall resolution.
It's fairly straight forward to improve the resolution of a good Dac by 2, 3
or even 4 bits using PWM, see Tom's description of how this is done in a
Z3801A on leapsecond.com.
So in short, one could use two identical 16 bit dacs, scale the resistors so
that only the upper 6 - 7 bits are used as a coarsedac, and use the fine dac
as a 20 bit dac with PWM resolution-enhancement (16 to 20 bits). This would
yield more than 26 bits theoretically from 2 inexpensive 16 bit dacs, and the
noise could be removed by low pass filtering using an analog filter with say
less than 0.3Hz cutoff frequency similar to the Z3801A circuitry. In this
case the coarsedac can probably even be exchanged for a simple high-stability
pot.
It does require a bit of real time firmware to do the PWM enhancement of
course.
bye,
Said
In a message dated 12/1/2008 22:47:29 Pacific Standard Time,
bruce.griffiths@xtra.co.nz writes:
The major advantage of such a DAC is the inherent monotonicity which
cannot be achieved and maintained (around coarse DAC transitions)
without frequent calibration when the outputs of 2 16 bit DACs are combined.
Bruce
SAIDJACK@aol.com wrote:
Hi Bruce,
yup, I thought that circuit and it's claim to 32 bit resolution was over the
top too, I didn't actually read the details.
Coarsedac changes are an issue as you mentioned, but one can get around them
by scaling the two dacs in a way to only use a couple of bits from the
coarsedac, and operate most of the time using just the fine dac.
In principle embedded calibration of the errors at coarse DAC
transitions should be possible.
This is similar to a mechanical coarse adjustment (such as on the 10811A)
setting the approximate voltage range, with the EFC done by the fine dac.
If you use a 16 - 18 bit fine dac, and 6 - 8 bits of a coarse dac then this
works quite well, and with a low aging SC-cut crystal you may never see a
coarsedac change, while still having over 21+ bits of overall resolution.
It's fairly straight forward to improve the resolution of a good Dac by 2, 3
or even 4 bits using PWM, see Tom's description of how this is done in a
Z3801A on leapsecond.com.
Yes this can be made to work well, as can using sigma delta modulation
however one then needs a good random number generator for dithering the
loop quantiser to eliminate idle tones which are otherwise somewhat
problematic. The effect is very easy to simulate using Matlab or even by
writing some simple code.
Using a synchronous filtering technique simplifies the filtering
considerably. The usual sigma delta modulation techniques advocated to
increase DAC resolution don't work that well due to the idle tones they
generate.
So in short, one could use two identical 16 bit dacs, scale the resistors so
that only the upper 6 - 7 bits are used as a coarsedac, and use the fine dac
as a 20 bit dac with PWM resolution-enhancement (16 to 20 bits). This would
yield more than 26 bits theoretically from 2 inexpensive 16 bit dacs, and the
noise could be removed by low pass filtering using an analog filter with say
less than 0.3Hz cutoff frequency similar to the Z3801A circuitry. In this
case the coarsedac can probably even be exchanged for a simple high-stability
pot.
Synchronous filtering of the DAC output would result in much faster
settling times with low modulation artifacts.
It does require a bit of real time firmware to do the PWM enhancement of
course.
bye,
Said
The technique advocated in the article may have fewer artifacts due to
DAC settling time issues.
Its also a lot cheaper since very tight tolerance stable components
aren't required.
The output should also be somewhat quieter.
Bruce
In message bef.38541c00.36663b55@aol.com, SAIDJACK@aol.com writes:
Coarsedac changes are an issue as you mentioned, but one can get around them
by scaling the two dacs in a way to only use a couple of bits from the
coarsedac, and operate most of the time using just the fine dac.
If you are controlling this with a microcontroller, there is an alternative
you should consider:
Use only a single DAC and then PWM modulate its output, followed
by a low-pass filter.
--
Poul-Henning Kamp | UNIX since Zilog Zeus 3.20
phk@FreeBSD.ORG | TCP/IP since RFC 956
FreeBSD committer | BSD since 4.3-tahoe
Never attribute to malice what can adequately be explained by incompetence.
Poul-Henning Kamp wrote:
In message bef.38541c00.36663b55@aol.com, SAIDJACK@aol.com writes:
Coarsedac changes are an issue as you mentioned, but one can get around them
by scaling the two dacs in a way to only use a couple of bits from the
coarsedac, and operate most of the time using just the fine dac.
If you are controlling this with a microcontroller, there is an alternative
you should consider:
Use only a single DAC and then PWM modulate its output, followed
by a low-pass filter.
The trouble with this approach is the very long filter time constants
with 24 bit PWM.
Combining 2 16 bit PWM outputs requires relatively close tolerance
components.
A synchronous filter is far more effective.
Bruce
In message 4934FA4B.6040707@xtra.co.nz, Bruce Griffiths writes:
Use only a single DAC and then PWM modulate its output, followed
by a low-pass filter.
The trouble with this approach is the very long filter time constants
with 24 bit PWM.
You don't want 24bit PWM, you want to combine a normal DAC with
PWM modulation.
The disadvantage is that the result is not linear. But it is
monotonic and approximately the lower 4/5th of the distinct
combinations are practically useful.
Take the Analog Devices ADUC7026 ARM7 microcontroller as example:
It has a 12bit DAC of pretty decent quality and a 16 bit PWM running
at 42 MHz.
If you just use 10 PWM bits, that gives you a PWM frequency of 20kHz,
easily filtered to DC by simple means.
Modulate the DAC output with the PWM and you get 1,353,354 unique
settings of which about the first million is usable.
That's about 6 additional DAC bits with the added advantage, that
if you prioritize the PWM for the low bits, you will get better
step regularity than the DAC would give you.
(Didn't somebody say that Fluke used PWM methods in their voltage
calibrators ? Would make a lot of sense if they did...)
If you use 14 bit PWM you get a 1281 Hz PWM frequency,
requiring more careful filtering, but giving you 20,384,526
distinct output combinations, with usable linearity up to about
for the first 16 million combinations, so that is approximately
a 24 bit DAC.
Full 16 bit PWM results in 321 Hz PWM frequency which means tricky
and likely impractical filtering, but you get 86,616,948 distinct
output combinations of which you can use approximately 65 million,
so that is around a 26bit dac.
Or 12-20 nanovolts between steps, if you prefer.
The real trouble with this aproach, is that you get "interleaved
gears" like on a bike: you need either a (huge) table or a bit of
code to tell you what the neighboring codes are.
Fortunately, finding a neighboring code is pretty easy, as the
relevant searchspace is pretty limited, so for EFC control of
an OCXO this is not a practical problem.
Poul-Henning
--
Poul-Henning Kamp | UNIX since Zilog Zeus 3.20
phk@FreeBSD.ORG | TCP/IP since RFC 956
FreeBSD committer | BSD since 4.3-tahoe
Never attribute to malice what can adequately be explained by incompetence.
Poul-Henning Kamp wrote:
In message 4934FA4B.6040707@xtra.co.nz, Bruce Griffiths writes:
Use only a single DAC and then PWM modulate its output, followed
by a low-pass filter.
The trouble with this approach is the very long filter time constants
with 24 bit PWM.
You don't want 24bit PWM, you want to combine a normal DAC with
PWM modulation.
24 bit PWM can work well with synchronous filtering and a high frequency
PWM clock.
The disadvantage is that the result is not linear. But it is
monotonic and approximately the lower 4/5th of the distinct
combinations are practically useful.
Take the Analog Devices ADUC7026 ARM7 microcontroller as example:
It has a 12bit DAC of pretty decent quality and a 16 bit PWM running
at 42 MHz.
If you just use 10 PWM bits, that gives you a PWM frequency of 20kHz,
easily filtered to DC by simple means.
Modulate the DAC output with the PWM and you get 1,353,354 unique
settings of which about the first million is usable.
That's about 6 additional DAC bits with the added advantage, that
if you prioritize the PWM for the low bits, you will get better
step regularity than the DAC would give you.
(Didn't somebody say that Fluke used PWM methods in their voltage
calibrators ? Would make a lot of sense if they did...)
eg Fluke 5700A etc.
Fluke have a string of patents relating to PWM as used in their calibrators.
e.g.
US5402082
US4716398
One of which shows how to virtually eliminate integral nonlinearity due
to analog switch on resistance mismatch and on resistance modulation.
Improvements to these techniques are possible. However in an EFC DAC
integral nonlinearity isnt particularly critical, monotonicity is.
If you use 14 bit PWM you get a 1281 Hz PWM frequency,
requiring more careful filtering, but giving you 20,384,526
distinct output combinations, with usable linearity up to about
for the first 16 million combinations, so that is approximately
a 24 bit DAC.
Full 16 bit PWM results in 321 Hz PWM frequency which means tricky
and likely impractical filtering, but you get 86,616,948 distinct
output combinations of which you can use approximately 65 million,
so that is around a 26bit dac.
Adequate filtering relatively easy and practical if one uses a
synchronous filter.
Or 12-20 nanovolts between steps, if you prefer.
The real trouble with this aproach, is that you get "interleaved
gears" like on a bike: you need either a (huge) table or a bit of
code to tell you what the neighboring codes are.
Fortunately, finding a neighboring code is pretty easy, as the
relevant searchspace is pretty limited, so for EFC control of
an OCXO this is not a practical problem.
Poul-Henning
There is a transient EFC voltage error at coarse DAC transitions whilst
the fine DAC is adjusted to compensate for DAC mismatch error.
The reference noise and drift (not important if its slow enough) will
limit the achievable resolution.
In principle software compensation of thermal drift and aging is
possible however flicker noise will still be a limiting factor.
A quieter reference may be needed in critical cases where the OCXO noise
isn't dominant.
Bruce