Erik Kaashoek via time-nuts writes:

I used my HP3336:

10 MHz house-standard to HP3336-ref-in and TDC chan A

HP3336 set to 10MHz output, and that output to TDC chan B

TDC triggers on positive zero-crossing on both channels.

Then step the HP3336 through 360 degree of phase, plot set phase vs. TDC reading

Repeat more than once to judge how well it works for you.

If you /really/ want to get into the weeds, you need to feed both
input A & B on the TDC from their own phase-settable sig-gen, and
work your way through all of 360x360 degrees.

If you do that to a HP5370, you can measure that two very specific PCB
traces cross each other inside the 5370 :-)

Note that the HP3336 steps the phase relative to an arbitrary and
unpredictable starting phase, so you have to do all measurements in
one session.

In principle pretty much any sig-gen which can set the phase can
be used, possibly even the $10 "DDS chip on a PCB" from eBay, but
the spectral purity of the sig-gen output, in particular around the
zero-crossing is a very significant source of noise.

I always apply corrections in postprocessing.

--
Poul-Henning Kamp      | UNIX since Zilog Zeus 3.20
phk@FreeBSD.ORG        | TCP/IP since RFC 956
FreeBSD committer      | BSD since 4.3-tahoe
Never attribute to malice what can adequately be explained by incompetence.

Hi Erik,

On 2024-06-09 08:54, Erik Kaashoek via time-nuts wrote:

"Apparent pulling of clock". It is a well known fenomena that nearby
start will shift a stop pulse. It has limited counters of multiple
brands, and basic isolation of the two trigger-paths is needed. Lack of
isolation may come from ground-bounce in common power/ground connection,
and good decoupling caps can be part of that solution. Some vendors have
separated comparators to increase isolation between channels.

Through calibration mechanisms one can correct this, if one considers
the non-linearity be from the other pulse rather from the core clock.

To separate trigger-shift and clock-pull, measure the internal clock
output with a separate counter to see if you can observe a clock pull or
not. Most often there is none.

You can also experience similar leakage from your core clock and even
separately from reference clock if they are not the same. You need to
back out to the period of those clocks to separate.

You have a sawtooth shaped non-linearity. Could be waiting-jitter. You
should be able to simply apply a sawtooth of matching phase and period.
Once corrected

It does. I'm not convinced you actually have the actual clock pulled
thought.

So, start with "predicting" the sawtooth and remove that. As you can see
already from the graph it will not be perfect. Your big blurp mid-point
will be easier to understand after that.

You also have a slow modulation over the full long period. It's like the
shart spike in one direct is spread out in the other.

The spike in the middle seems to be a double derivate pattern. That's a
hint of the system-order of the leakage.

One potential test you can do is to have an input signal of bad
phase-noise. As you average, the finer-grained version of non-linearity
will average out and you can see the larger shapes pretty OK. It can be
a complementary approach. In fact, this is what the HP5328A/B was doing
with the right options, but by modulating the reference clock and
average out the non-linearities of quantization steps. I did a small
simulation and paper on that.

Anyway, hope you have use of my ramblings.

Cheers,
Magnus