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View all threadsFPGA hack newbie problems
Hello everyone,
I have an E100 capable of sampling at 21 MHz (according to itself), but I
need to sampla at atleast 60 MHz.
There is no need for continous sampling at this speed, the goal is to find
the dominating frequency which is fairly stable.
I need help/info/suggestions on:
- Where in the dataflow of the FPGA is it possible (least risk/work) to do
this re-packing of the ADC stream? - Is the FPGA cruicial to the operation of the E100 (will it die with the
FPGA)? Or will a rotten FPGA image just spoil the sampling ability? - Where do I put the FPGA configuration file, and in what format, to have
it loaded into the FPGA?
Kind regards
Peter J
On Thu, Jul 19, 2012 at 2:48 AM, Peter Janhäll spejan@gmail.com wrote:
Hello everyone,
I have an E100 capable of sampling at 21 MHz (according to itself), but I
need to sampla at atleast 60 MHz.
There is no need for continous sampling at this speed, the goal is to find
the dominating frequency which is fairly stable.
I need help/info/suggestions on:
- Where in the dataflow of the FPGA is it possible (least risk/work) to
do this re-packing of the ADC stream?
I suggest you start by looking at the custom/ directory in the UHD fpga
source, specifically custom_dsp_rx.v and custom_engine_rx.v. We've
implemented the ability to compile custom modules which can be used for
this sort of thing.
- Is the FPGA cruicial to the operation of the E100 (will it die with the
FPGA)? Or will a rotten FPGA image just spoil the sampling ability?
The latter. The processing is all on the Gumstix Overo board. The FPGA is
used exclusively for DSP-related tasks. However, it's possible a bad FPGA
image could stomp on the GPMC bus shared with the Ethernet controller and
gum up your Ethernet connection.
- Where do I put the FPGA configuration file, and in what format, to have
it loaded into the FPGA?
You can specify that in the UHD source/sink arguments. I.e.:
wat = uhd.single_usrp_source("fpga=my_fpga_image.bin",
uhd.io_type_t.COMPLEX_FLOAT32, 1)
The examples included with UHD pass args in via the --args parameter, so
you can say:
rx_samples_to_file --args=fpga=my_fpga_image.bin
--n
Kind regards
Peter J
USRP-users mailing list
USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Thanks a lot for the answers, which produced the follwing questions:
- I found the custom wedges, but no reference to them (using MS explorer).
(Except for CUSTOM_SRCS in Makefile.E100).
Where do they fit? - Is the FPGA reconfigured for each call of uhd::usrp::multi_usrp::make()
? Does this explain the start delay?
I couldn't find the single_usrp_source() in the Doxygen database.
Regards
Peter J
2012/7/19 Nick Foster nick@ettus.com
On Thu, Jul 19, 2012 at 2:48 AM, Peter Janhäll spejan@gmail.com wrote:
Hello everyone,
I have an E100 capable of sampling at 21 MHz (according to itself), but I
need to sampla at atleast 60 MHz.
There is no need for continous sampling at this speed, the goal is to
find the dominating frequency which is fairly stable.
I need help/info/suggestions on:
- Where in the dataflow of the FPGA is it possible (least risk/work) to
do this re-packing of the ADC stream?
I suggest you start by looking at the custom/ directory in the UHD fpga
source, specifically custom_dsp_rx.v and custom_engine_rx.v. We've
implemented the ability to compile custom modules which can be used for
this sort of thing.
- Is the FPGA cruicial to the operation of the E100 (will it die with
the FPGA)? Or will a rotten FPGA image just spoil the sampling ability?
The latter. The processing is all on the Gumstix Overo board. The FPGA is
used exclusively for DSP-related tasks. However, it's possible a bad FPGA
image could stomp on the GPMC bus shared with the Ethernet controller and
gum up your Ethernet connection.
- Where do I put the FPGA configuration file, and in what format, to
have it loaded into the FPGA?
You can specify that in the UHD source/sink arguments. I.e.:
wat = uhd.single_usrp_source("fpga=my_fpga_image.bin",
uhd.io_type_t.COMPLEX_FLOAT32, 1)
The examples included with UHD pass args in via the --args parameter, so
you can say:
rx_samples_to_file --args=fpga=my_fpga_image.bin
--n
Kind regards
Peter J
USRP-users mailing list
USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
On 07/19/2012 01:29 PM, Peter Janhäll wrote:
Thanks a lot for the answers, which produced the follwing questions:
- I found the custom wedges, but no reference to them (using MS explorer).
(Except for CUSTOM_SRCS in Makefile.E100).
Where do they fit?
There is an empty CUSTOM_SRCS in each top level makefile:
find -name "Makefile*" | xargs grep CUSTOM_SRCS
./top/N2x0/Makefile.N200R3:CUSTOM_SRCS =
./top/N2x0/Makefile.N200R4:CUSTOM_SRCS =
./top/N2x0/Makefile.N210R3:CUSTOM_SRCS =
./top/N2x0/Makefile.N210R4:CUSTOM_SRCS =
./top/USRP2/Makefile:CUSTOM_SRCS =
./top/E1x0/Makefile.E110:CUSTOM_SRCS =
./top/E1x0/Makefile.E100:CUSTOM_SRCS =
./top/B100/Makefile.B100:CUSTOM_SRCS =
Just make a copy of the makefile for you design and set CUSTOM_SRCS with
a list of paths to your new verilog files. A possible example of setting
such a variable, you might look here:
- Is the FPGA reconfigured for each call of uhd::usrp::multi_usrp::make()
? Does this explain the start delay?
The FPGA configuration is very fast on E100. I think you are seeing
delay of clock configuration and check for lock, and even more so, the
timeout looking for GPSDO.
I will be pushing code soon to the next branch where the E100 caches the
result of looking for the GPSDO so it doesnt look every time.
I couldn't find the single_usrp_source() in the Doxygen database.
The source and sink blocks are gnuradio wrappers
http://gnuradio.org/cgit/gnuradio.git/tree/gr-uhd/include/
And this is the doxygen page for the UHD API:
http://files.ettus.com/uhd_docs/doxygen/html/classuhd_1_1usrp_1_1multi__usrp.html
-josh