Hi, I am trying a study on the receiver architecture of the USRP N-210. In order to run the simulation in ModelSim, I wish to know the correct top-level file. In the path /fpga/usrp2/top, there are lots of folders namely: 1. u2plus 2. u2_rev3 3. u2_rev3_iad 4. u2_rev3_2rx_iad Please could someone tell me the exact top-level file and associated testbench for the receiver part as well the overall fpga in order to get the bit image. This is to be done before I can add more parts to the existing code. Thanks a lot Regards Rithvic

On 05/04/2011 09:59 PM, rithvic rajah wrote: > > Hi, > > I am trying a study on the receiver architecture of the USRP N-210. > In order to run the simulation in ModelSim, I wish to know the > correct top-level file. In the path /fpga/usrp2/top, there are lots > of folders namely: > > 1. u2plus 2. u2_rev3 3. u2_rev3_iad 4. u2_rev3_2rx_iad > > Please could someone tell me the exact top-level file and associated > testbench for the receiver part as well the overall fpga in order to > get the bit image. This is to be done before I can add more parts to > the existing code. > This should help you map makefiles to products: http://code.ettus.com/redmine/ettus/projects/uhd/repository/revisions/master/entry/images/Makefile -josh > Thanks a lot > > Regards Rithvic > > > > _______________________________________________ USRP-users mailing > list USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com