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Si5351 configuration propagation delays ?

D
Dave
Fri, Mar 17, 2023 1:13 PM

I am using an Si5351 to generate 10MHz and 20MHz clocks and using the
PLLA "correction" divider register to adjust the input clock (a TCXO) to
be accurately 25MHz.

Does anyone know how long it takes for the outputs to be stable after a
change to the calibration register (it also requires the output
frequencies to be re-calculated).

Is it of the order of milliseconds or seconds ??

I have trawled through the data-sheets and app notes but I cannot find
anything.

Regards,
Dave

I am using an Si5351 to generate 10MHz and 20MHz clocks and using the PLLA "correction" divider register to adjust the input clock (a TCXO) to be accurately 25MHz. Does anyone know how long it takes for the outputs to be stable after a change to the calibration register (it also requires the output frequencies to be re-calculated). Is it of the order of milliseconds or seconds ?? I have trawled through the data-sheets and app notes but I cannot find anything. Regards, Dave
EK
Erik Kaashoek
Fri, Mar 17, 2023 2:11 PM

Dave,
Should be below 1 ms.
With the SI5351 you have the fractional PLL with its registers and a per
output channel fractional divider.
Changing the fractional output divider does not require the pll to
acquire lock so it is very fast.
The PLL itself locks fast, its possible to sweep 1000 frequencies within
1 second.
For practical experience, check how fast a nanoVNA-H4 or nanoVNA-H can
do a sweep. When sweeping below 100MHz this time includes the setting up
of two output fractional dividers
I've implemented a GPSDO using a OCXO as input to the SI5351 and using
the SI5351 to do the frequency adjustments.
To get best resolution (mHz) the setting was created using a search for
the best combination of PLL and output divider
Big problem with this setup are the phase/frequency  jumps you get with
each new settings of the SI5351. A VC-OCXO will "slowly" move to a new
frequency.
Erik.

On 17-3-2023 14:13, Dave via time-nuts wrote:

I am using an Si5351 to generate 10MHz and 20MHz clocks and using the
PLLA "correction" divider register to adjust the input clock (a TCXO)
to be accurately 25MHz.

Does anyone know how long it takes for the outputs to be stable after
a change to the calibration register (it also requires the output
frequencies to be re-calculated).

Is it of the order of milliseconds or seconds ??

I have trawled through the data-sheets and app notes but I cannot find
anything.

Regards,
Dave


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Dave, Should be below 1 ms. With the SI5351 you have the fractional PLL with its registers and a per output channel fractional divider. Changing the fractional output divider does not require the pll to acquire lock so it is very fast. The PLL itself locks fast, its possible to sweep 1000 frequencies within 1 second. For practical experience, check how fast a nanoVNA-H4 or nanoVNA-H can do a sweep. When sweeping below 100MHz this time includes the setting up of two output fractional dividers I've implemented a GPSDO using a OCXO as input to the SI5351 and using the SI5351 to do the frequency adjustments. To get best resolution (mHz) the setting was created using a search for the best combination of PLL and output divider Big problem with this setup are the phase/frequency  jumps you get with each new settings of the SI5351. A VC-OCXO will "slowly" move to a new frequency. Erik. On 17-3-2023 14:13, Dave via time-nuts wrote: > I am using an Si5351 to generate 10MHz and 20MHz clocks and using the > PLLA "correction" divider register to adjust the input clock (a TCXO) > to be accurately 25MHz. > > Does anyone know how long it takes for the outputs to be stable after > a change to the calibration register (it also requires the output > frequencies to be re-calculated). > > Is it of the order of milliseconds or seconds ?? > > I have trawled through the data-sheets and app notes but I cannot find > anything. > > Regards, > Dave > > _______________________________________________ > time-nuts mailing list -- time-nuts@lists.febo.com > To unsubscribe send an email to time-nuts-leave@lists.febo.com