|                                                        |
         ---------- strobe ---<<<---------------

i understand. I still have a question regarding the RX chain. I find strobe (ready) and sample (data) going from dsp_core_rx0 to vita_rx_chain0 and run (valid) going from vita_rx_chain0 to dsp_core_rx0. if i read well the avalon spec, run (valid) should go from source to sink and strobe (ready) from sink to source. But in the rx chain it's the opposite. Why ? what does it change for the transfer ? regards. Christophe ALEXANDRE Conservatoire National des Arts et Métiers (CNAM) Laboratoire CEDRIC-LAETITIA Département EASY Accès 17-1-32, Case 2D2P10 292 rue Saint Martin 75141 PARIS CEDEX 03 FRANCE email : christophe.alexandre@cnam.fr tel. 0140272699 fax. 0140272994 ----- Original Message ----- From: "Josh Blum" <josh@ettus.com> To: "ALEXANDRE Christophe" <christophe.alexandre@cnam.fr> Sent: Friday, September 16, 2011 7:35 PM Subject: Re: [USRP-users] E100 : VHDL IP insertion in existing FPGA design > > > On 09/16/2011 01:29 PM, ALEXANDRE Christophe wrote: >> what is the readyLatency in dsp_core_tx ? >> >> regards. >> > > So that would be a zero cycle delay. Meaning: > > The sample is valid on the same cycle where run is high. > >> >> Christophe ALEXANDRE >> Conservatoire National des Arts et Métiers (CNAM) >> Laboratoire CEDRIC-LAETITIA >> Département EASY >> Accès 17-1-32, Case 2D2P10 >> 292 rue Saint Martin >> 75141 PARIS CEDEX 03 >> FRANCE >> email : christophe.alexandre@cnam.fr >> tel. 0140272699 >> fax. 0140272994 >> >> >> ----- Original Message ----- From: "Josh Blum" <josh@ettus.com> >> To: "ALEXANDRE Christophe" <christophe.alexandre@cnam.fr> >> Cc: <usrp-users@lists.ettus.com> >> Sent: Friday, September 16, 2011 6:46 PM >> Subject: Re: [USRP-users] E100 : VHDL IP insertion in existing FPGA >> design >> >> >>> >>> >>> On 09/16/2011 12:41 PM, ALEXANDRE Christophe wrote: >>>> Hi josh, >>>> >>>> i have some difficulties to understand the protocol >>>> between vita_tx_control and dsp_core_tx. What i see is : >>>> >>>> ------------------- sample, run ---------------- >>>> vita_tx_control | -----------------> | dsp_core_tx | ----> >>>> ------------------- ---------------- >>>> | | >>>> ---------- strobe ---<<<--------------- >>>> >>>> - sample and run comes from vita_tx_control and go to >>>> dsp_core_tx. >>>> >>>> - but strobe comes from dsp_core_tx and go back to >>>> vita_tx_control. >>>> >>>> can you explain how the sample is transfered using these >>>> signals ? >>>> >>> >>> Its essentially avalon streaming, where run = valid and strobe = ready >>> >>> www.altera.com/literature/manual/mnl_avalon_spec.pdf >>> >>> -josh >>> >>

On 09/16/2011 02:48 PM, ALEXANDRE Christophe wrote: > i understand. I still have a question > regarding the RX chain. I find strobe (ready) > and sample (data) going from dsp_core_rx0 > to vita_rx_chain0 and run (valid) going from > vita_rx_chain0 to dsp_core_rx0. > > if i read well the avalon spec, run (valid) should go > from source to sink and strobe (ready) from sink to source. > But in the rx chain it's the opposite. Why ? > I agree, the naming convention needs to be fixed. I believe Matt is working on this very task actually this week. :-) So, to explain the confusion... I believe the naming convention is centric to the directionality between rf and host, rather than the producer/consumer model. Think about it this way, there are two control signals: Only one control signal makes sense to be "valid" and only one makes sense to be "ready". -josh

is there any way to simulate the tranfer cycle and get a chronogram ? regards. Christophe ALEXANDRE Conservatoire National des Arts et Métiers (CNAM) Laboratoire CEDRIC-LAETITIA Département EASY Accès 17-1-32, Case 2D2P10 292 rue Saint Martin 75141 PARIS CEDEX 03 FRANCE email : christophe.alexandre@cnam.fr tel. 0140272699 fax. 0140272994 ----- Original Message ----- From: "Josh Blum" <josh@ettus.com> To: "ALEXANDRE Christophe" <christophe.alexandre@cnam.fr> Cc: <usrp-users@lists.ettus.com> Sent: Friday, September 16, 2011 9:00 PM Subject: Re: [USRP-users] E100 : VHDL IP insertion in existing FPGA design > > > On 09/16/2011 02:48 PM, ALEXANDRE Christophe wrote: >> i understand. I still have a question >> regarding the RX chain. I find strobe (ready) >> and sample (data) going from dsp_core_rx0 >> to vita_rx_chain0 and run (valid) going from >> vita_rx_chain0 to dsp_core_rx0. >> >> if i read well the avalon spec, run (valid) should go >> from source to sink and strobe (ready) from sink to source. >> But in the rx chain it's the opposite. Why ? >> > > I agree, the naming convention needs to be fixed. I believe Matt is > working on this very task actually this week. :-) > > So, to explain the confusion... > I believe the naming convention is centric to the directionality between > rf and host, rather than the producer/consumer model. > > Think about it this way, there are two control signals: Only one control > signal makes sense to be "valid" and only one makes sense to be "ready". > > -josh >

On 09/16/2011 04:01 PM, ALEXANDRE Christophe wrote: > is there any way to simulate > the tranfer cycle and get a chronogram ? I would bring the signals you are interested in to the debug connector and look at them with a logic analyzer. Philip > > regards. > > > Christophe ALEXANDRE > Conservatoire National des Arts et Métiers (CNAM) > Laboratoire CEDRIC-LAETITIA > Département EASY > Accès 17-1-32, Case 2D2P10 > 292 rue Saint Martin > 75141 PARIS CEDEX 03 > FRANCE > email : christophe.alexandre@cnam.fr > tel. 0140272699 > fax. 0140272994 > > > ----- Original Message ----- From: "Josh Blum" <josh@ettus.com> > To: "ALEXANDRE Christophe" <christophe.alexandre@cnam.fr> > Cc: <usrp-users@lists.ettus.com> > Sent: Friday, September 16, 2011 9:00 PM > Subject: Re: [USRP-users] E100 : VHDL IP insertion in existing FPGA design > > >> >> >> On 09/16/2011 02:48 PM, ALEXANDRE Christophe wrote: >>> i understand. I still have a question >>> regarding the RX chain. I find strobe (ready) >>> and sample (data) going from dsp_core_rx0 >>> to vita_rx_chain0 and run (valid) going from >>> vita_rx_chain0 to dsp_core_rx0. >>> >>> if i read well the avalon spec, run (valid) should go >>> from source to sink and strobe (ready) from sink to source. >>> But in the rx chain it's the opposite. Why ? >>> >> >> I agree, the naming convention needs to be fixed. I believe Matt is >> working on this very task actually this week. :-) >> >> So, to explain the confusion... >> I believe the naming convention is centric to the directionality between >> rf and host, rather than the producer/consumer model. >> >> Think about it this way, there are two control signals: Only one control >> signal makes sense to be "valid" and only one makes sense to be "ready". >> >> -josh >> > > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >

On 09/16/2011 04:01 PM, ALEXANDRE Christophe wrote: > is there any way to simulate > the tranfer cycle and get a chronogram ? > If you want pure verilog simulation, you can make a custom top level block, and use a tool like icarus to compile the simulation files. The files in the fpga tree that end in _top.v are all mini-simulations for various parts of the code. Use them as examples for a simulation top-block. -josh > regards. > > > Christophe ALEXANDRE > Conservatoire National des Arts et Métiers (CNAM) > Laboratoire CEDRIC-LAETITIA > Département EASY > Accès 17-1-32, Case 2D2P10 > 292 rue Saint Martin > 75141 PARIS CEDEX 03 > FRANCE > email : christophe.alexandre@cnam.fr > tel. 0140272699 > fax. 0140272994 > > > ----- Original Message ----- From: "Josh Blum" <josh@ettus.com> > To: "ALEXANDRE Christophe" <christophe.alexandre@cnam.fr> > Cc: <usrp-users@lists.ettus.com> > Sent: Friday, September 16, 2011 9:00 PM > Subject: Re: [USRP-users] E100 : VHDL IP insertion in existing FPGA design > > >> >> >> On 09/16/2011 02:48 PM, ALEXANDRE Christophe wrote: >>> i understand. I still have a question >>> regarding the RX chain. I find strobe (ready) >>> and sample (data) going from dsp_core_rx0 >>> to vita_rx_chain0 and run (valid) going from >>> vita_rx_chain0 to dsp_core_rx0. >>> >>> if i read well the avalon spec, run (valid) should go >>> from source to sink and strobe (ready) from sink to source. >>> But in the rx chain it's the opposite. Why ? >>> >> >> I agree, the naming convention needs to be fixed. I believe Matt is >> working on this very task actually this week. :-) >> >> So, to explain the confusion... >> I believe the naming convention is centric to the directionality between >> rf and host, rather than the producer/consumer model. >> >> Think about it this way, there are two control signals: Only one control >> signal makes sense to be "valid" and only one makes sense to be "ready". >> >> -josh >> >