Hi, 
Guest
Pic
Sign In

Search results for all lists

10000 messages found
Sort by
List: great-loop@lists.trawlering.com
From: Charles Culotta
 
[TWGL] Re: TWL: Support Your Local (US) Power Squadron
Thu, Dec 20, 2001 12:54 AM
tlined to him which were gleaned by me from the posts. Of course the problem areas will not be rectified overnight but they will be addressed. I am heartened by his words and actions and hope that those of you who have had some difficulty to please try again as GOOD MEMBERS are hard to come by for any service organization particularly for one like USPS that takes on so many projects. CCC LETS ROLL! Charles and Pat Culotta Patterson, La. Web Site: http://www.geocities.com/charlesculotta/
List: usrp-users@lists.ettus.com
From: Lamar Owen
 
Re: [USRP-users] UHD version that supports older DBSRX on a USRP1.
Mon, Nov 16, 2020 8:32 PM
master/host/lib/usrp/dboard/db_dbsrx.cpp > along about line 302.  Am I barking up the wrong tree, or if the 'for > (auto ....' construct needed changing in one case it needs changing in > this case, too?  I'll need to move from the conda package to the EPEL8 > RPM package, because I know how to rebuild those and can test patches > with those.  I don't know enough c++ to be able to generate the patch, > though. Just in case this helps, here's logging output: (base) [pari-sdr@dhcp-pool167 ~]$ UHD_LOG_CONSOLE_LEVEL=0 uhd_usrp_probe [INFO] [UHD] linux; GNU C++ version 7.5.0; Boost_107400; UHD_3.15.0.HEAD-release [DEBUG] [MPMD] Discovering MPM devices on port 49600 [DEBUG] [MPMD] Discovering MPM devices on port 49600 [DEBUG] [MPMD] Discovering MPM devices on port 49600 [TRACE] [UDP] Creating udp transport for 127.255.255.255 49600 [TRACE] [UDP] Creating udp transport for 192.168.122.255 49600 [TRACE] [UDP] Creating udp transport for 192.168.1.255 49600 [DEBUG] [USRP1] USRP1 firmware image: /home/pari-sdr/anaconda3/share/uhd/images/usrp1_fw.ihx [TRACE] [UDP] Creating udp transport for 192.168.1.255 49152 [TRACE] [UDP] Creating udp transport for 192.168.122.255 49152 [TRACE] [UDP] Creating udp transport for 192.168.1.255 49152 [TRACE] [UDP] Creating udp transport for 192.168.122.255 49152 [TRACE] [NIRIO] rpc_client connection request cancelled/aborted. [TRACE] [UDP] Creating udp transport for 192.168.1.255 49152 [TRACE] [UDP] Creating udp transport for 192.168.122.255 49152 [TRACE] [UDP] Creating udp transport for 192.168.1.255 50000 [TRACE] [UDP] Creating udp transport for 192.168.122.255 50000 [TRACE] [UHD] Device hash: 6433317707856818692 [DEBUG] [PREFS] Loaded system config file /etc/uhd/uhd.conf [DEBUG] [PREFS] Loaded user config file /home/pari-sdr/.uhd/uhd.conf [INFO] [USRP1] Opening a USRP1 device... [DEBUG] [USRP1] USRP1 FPGA image: /home/pari-sdr/anaconda3/share/uhd/images/usrp1_fpga.rbf [TRACE] [USRP1] poke32(13, 0x       0) [TRACE] [USRP1] poke32(14, 0x       0) [TRACE] [USRP1] peek32( 3) [TRACE] [USRP1] peek32( 3) [TRACE] [USRP1] peek32( 3) [TRACE] [USRP1] peek32( 3) [DEBUG] [USRP1] USRP1 Capabilities    number of duc's: 2    number of ddc's: 2    rx halfband:     1    tx halfband:     0 [INFO] [USRP1] Using FPGA clock rate of 64.000000MHz... [TRACE] [USRP1] codec control write reg: 0x      20 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 32  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x       0 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 0  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     106 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 262  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     280 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 640  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     380 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 896  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     400 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 1024  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     504 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 1284  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     608 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 1544  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     700 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 1792  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     800 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 2048  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     900 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 2304  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     a00 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 2560  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     b00 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 2816  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     c00 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 3072  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     d00 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 3328  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     ec0 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 3776  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     fc0 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 4032  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    10c7 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 4295  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1100 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 4352  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1249 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 4681  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1312 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 4882  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1410 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 5136  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1500 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 5376  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1600 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 5632  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1700 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 5888  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1849 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 6217  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1940 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 6464  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    2209 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 8713  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     280 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 640  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     380 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 896  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    10ff [TRACE] [USRP1] transact_spi:   slave: 2  bits: 4351  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x      20 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 32  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x       0 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 0  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     106 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 262  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     280 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 640  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     380 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 896  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     400 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 1024  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     504 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 1284  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     608 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 1544  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     700 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 1792  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     800 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 2048  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     900 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 2304  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     a00 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 2560  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     b00 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 2816  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     c00 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 3072  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     d00 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 3328  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     ec0 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 3776  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     fc0 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 4032  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    10c7 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 4295  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1100 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 4352  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1249 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 4681  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1312 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 4882  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1410 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 5136  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1500 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 5376  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1600 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 5632  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1700 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 5888  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1849 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 6217  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1940 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 6464  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    2209 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 8713  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     280 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 640  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     380 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 896  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    10ff [TRACE] [USRP1] transact_spi:   slave: 4  bits: 4351  num_bits: 16 readback: 0 [TRACE] [USRP1] poke32(16, 0x       0) [TRACE] [USRP1] poke32(17, 0x       0) [TRACE] [USRP1] poke32(15, 0x       3) [TRACE] [USRP1] poke32(18, 0x       0) [TRACE] [USRP1] poke32(19, 0x       0) [TRACE] [USRP1] poke32(15, 0x       f) [TRACE] [USRP1] peek32( 3) [TRACE] [USRP1] peek32( 3) [TRACE] [USRP1] peek32( 3) [TRACE] [USRP1] peek32( 3) [TRACE] [USRP1] peek32( 3) [TRACE] [USRP1] peek32( 3) [TRACE] [USRP1] poke32( 6, 0xffff0000) [TRACE] [USRP1] poke32(10, 0xffff0000) [TRACE] [USRP1] poke32(23, 0x       0) [TRACE] [USRP1] poke32( 5, 0xffff0000) [TRACE] [USRP1] poke32( 9, 0xffff0000) [TRACE] [USRP1] poke32(20, 0x       0) [TRACE] [DBSRX] DBSRX: send reg 0x00, value 0x0003, start_addr = 0x0000, num_bytes 3 [TRACE] [DBSRX] DBSRX: send reg 0x01, value 0x00b6, start_addr = 0x0000, num_bytes 3 [TRACE] [DBSRX] DBSRX: send reg 0x02, value 0x003d, start_addr = 0x0000, num_bytes 3 [TRACE] [DBSRX] DBSRX: send reg 0x03, value 0x007f, start_addr = 0x0003, num_bytes 3 [TRACE] [DBSRX] DBSRX: send reg 0x04, value 0x0002, start_addr = 0x0003, num_bytes 3 [TRACE] [DBSRX] DBSRX: send reg 0x05, value 0x001f, start_addr = 0x0003, num_bytes 3 [TRACE] [DBSRX] DBSRX GC1 Gain: 0.000000 dB, dac_volts: 2.700000 V [TRACE] [USRP1] codec control write reg: 0x    24d1 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 9425  num_bits: 16 readback: 0 [TRACE] [DBSRX] DBSRX GC2 Gain: 0.000000 dB, reg: 31 [TRACE] [DBSRX] DBSRX: send reg 0x05, value 0x001f, start_addr = 0x0005, num_bytes 1 [TRACE] [USRP1] poke32(23, 0x       0) [TRACE] [USRP1] poke32( 6, 0xffff0001) [TRACE] [DBSRX] DBSRX: trying ref_clock 4000000.000000 and m_divider 4 [TRACE] [DBSRX] DBSRX R:2 [ERROR] [DBMGR] The daughterboard manager encountered a recoverable error in init. Loading the "unknown" daughterboard implementations to continue. The daughterboard cannot operate until this error is resolved. AssertionError: m and ref_clock/m >= 1e6 and ref_clock/m <= 2.5e6   in double dbsrx::set_lo_freq(double)   at /home/conda/feedstock_root/build_artifacts/uhd_1602712704625/work/host/lib/usrp/dboard/db_dbsrx.cpp:306 [TRACE] [USRP1] poke32( 6, 0xffff0000) [TRACE] [USRP1] poke32(10, 0xffff0000) [TRACE] [USRP1] poke32(23, 0x       0) [TRACE] [USRP1] poke32( 5, 0xffff0000) [TRACE] [USRP1] poke32( 9, 0xffff0000) [TRACE] [USRP1] poke32(20, 0x       0) [TRACE] [USRP1] poke32( 8, 0xffff0000) [TRACE] [USRP1] poke32(12, 0xffff0000) [TRACE] [USRP1] poke32(29, 0x       0) [TRACE] [USRP1] poke32( 7, 0xffff0000) [TRACE] [USRP1] poke32(11, 0xffff0000) [TRACE] [USRP1] poke32(26, 0x       0) [TRACE] [USRP1] codec control write reg: 0x     808 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 2056  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     808 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 2056  num_bits: 16 readback: 0 [TRACE] [USRP1] peek32( 3) [TRACE] [USRP1] peek32( 3) [TRACE] [USRP1] poke32( 1, 0x       1) [TRACE] [USRP1] poke32(33, 0x      1f) [TRACE] [USRP1] peek32( 3) [TRACE] [USRP1] peek32( 3) [TRACE] [USRP1] peek32( 3) [TRACE] [USRP1] peek32( 3) [TRACE] [USRP1] poke32( 0, 0x       1) [TRACE] [USRP1] poke32(32, 0x      1f) [TRACE] [USRP1] peek32( 3) [TRACE] [USRP1] peek32( 3) [TRACE] [USRP1] poke32(34, 0x       0) [TRACE] [USRP1] poke32(35, 0x       0) [TRACE] [USRP1] poke32(38, 0x      41) [TRACE] [USRP1] poke32(39, 0x     981)   _____________________________________________________  / |       Device: USRP1 Device |     _____________________________________________________ |    / |   |       Mboard: USRP1 |   |   serial: 4460cd30 |   | |   |   Time sources:  none |   |   Clock sources: internal |   |   Sensors: |   |     _____________________________________________________ |   |    / |   |   |       RX DSP: 0 |   |   | |   |   |   Freq range: -32.000 to 32.000 MHz |   |     _____________________________________________________ |   |    / |   |   |       RX DSP: 1 |   |   | |   |   |   Freq range: -32.000 to 32.000 MHz |   |     _____________________________________________________ |   |    / |   |   |       RX Dboard: A |   |   |   ID: DBSRX (0x0002) |   |   |     _____________________________________________________ |   |   |    / |   |   |   |       RX Frontend: 0 |   |   |   |   Name: Unknown (0xffff) - 0 |   |   |   |   Antennas: |   |   |   |   Sensors: |   |   |   |   Freq range: 0.000 to 0.000 MHz |   |   |   |   Gain Elements: None |   |   |   |   Bandwidth range: 0.0 to 0.0 step 0.0 Hz |   |   |   |   Connection Type: IQ |   |   |   |   Uses LO offset: No |   |   |     _____________________________________________________ |   |   |    / |   |   |   |       RX Codec: A |   |   |   |   Name: ad9522 |   |   |   |   Gain range pga: 0.0 to 20.0 step 1.0 dB |   |     _____________________________________________________ |   |    / |   |   |       RX Dboard: B |   |   |     _____________________________________________________ |   |   |    / |   |   |   |       RX Frontend: 0 |   |   |   |   Name: Unknown (0xffff) - 0 |   |   |   |   Antennas: |   |   |   |   Sensors: |   |   |   |   Freq range: 0.000 to 0.000 MHz |   |   |   |   Gain Elements: None |   |   |   |   Bandwidth range: 0.0 to 0.0 step 0.0 Hz |   |   |   |   Connection Type: IQ |   |   |   |   Uses LO offset: No |   |   |     _____________________________________________________ |   |   |    / |   |   |   |       RX Codec: B |   |   |   |   Name: ad9522 |   |   |   |   Gain range pga: 0.0 to 20.0 step 1.0 dB |   |     _____________________________________________________ |   |    / |   |   |       TX DSP: 0 |   |   | |   |   |   Freq range: -44.000 to 44.000 MHz |   |     _____________________________________________________ |   |    / |   |   |       TX DSP: 1 |   |   | |   |   |   Freq range: -44.000 to 44.000 MHz |   |     _____________________________________________________ |   |    / |   |   |       TX Dboard: A |   |   |     _____________________________________________________ |   |   |    / |   |   |   |       TX Frontend: 0 |   |   |   |   Name: Unknown (0xffff) - 0 |   |   |   |   Antennas: |   |   |   |   Sensors: |   |   |   |   Freq range: 0.000 to 0.000 MHz |   |   |   |   Gain Elements: None |   |   |   |   Bandwidth range: 0.0 to 0.0 step 0.0 Hz |   |   |   |   Connection Type: IQ |   |   |   |   Uses LO offset: No |   |   |     _____________________________________________________ |   |   |    / |   |   |   |       TX Codec: A |   |   |   |   Name: ad9522 |   |   |   |   Gain range pga: -20.0 to 0.0 step 0.1 dB |   |     _____________________________________________________ |   |    / |   |   |       TX Dboard: B |   |   |     _____________________________________________________ |   |   |    / |   |   |   |       TX Frontend: 0 |   |   |   |   Name: Unknown (0xffff) - 0 |   |   |   |   Antennas: |   |   |   |   Sensors: |   |   |   |   Freq range: 0.000 to 0.000 MHz |   |   |   |   Gain Elements: None |   |   |   |   Bandwidth range: 0.0 to 0.0 step 0.0 Hz |   |   |   |   Connection Type: IQ |   |   |   |   Uses LO offset: No |   |   |     _____________________________________________________ |   |   |    / |   |   |   |       TX Codec: B |   |   |   |   Name: ad9522 |   |   |   |   Gain range pga: -20.0 to 0.0 step 0.1 dB [TRACE] [USRP1] codec control write reg: 0x     808 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 2056  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     808 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 2056  num_bits: 16 readback: 0 [TRACE] [USRP1] poke32( 6, 0xffff0000) [TRACE] [USRP1] poke32(10, 0xffff0000) [TRACE] [USRP1] poke32(23, 0x       0) [TRACE] [USRP1] poke32( 5, 0xffff0000) [TRACE] [USRP1] poke32( 9, 0xffff0000) [TRACE] [USRP1] poke32(20, 0x       0) [TRACE] [USRP1] poke32( 8, 0xffff0000) [TRACE] [USRP1] poke32(12, 0xffff0000) [TRACE] [USRP1] poke32(29, 0x       0) [TRACE] [USRP1] poke32( 7, 0xffff0000) [TRACE] [USRP1] poke32(11, 0xffff0000) [TRACE] [USRP1] poke32(26, 0x       0) [TRACE] [USRP1] codec control write reg: 0x    2400 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 9216  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    2500 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 9472  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    2600 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 9728  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    2a00 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 10752  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    2b00 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 11008  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     107 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 263  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     80f [TRACE] [USRP1] transact_spi:   slave: 2  bits: 2063  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    2400 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 9216  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    2500 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 9472  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    2600 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 9728  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    2a00 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 10752  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    2b00 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 11008  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     107 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 263  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     80f [TRACE] [USRP1] transact_spi:   slave: 4  bits: 2063  num_bits: 16 readback: 0 (base) [pari-sdr@dhcp-pool167 ~]$ And with a second USRP1: (base) [pari-sdr@dhcp-pool167 ~]$ UHD_LOG_CONSOLE_LEVEL=0 uhd_usrp_probe [INFO] [UHD] linux; GNU C++ version 7.5.0; Boost_107400; UHD_3.15.0.HEAD-release [DEBUG] [MPMD] Discovering MPM devices on port 49600 [DEBUG] [MPMD] Discovering MPM devices on port 49600 [TRACE] [UDP] Creating udp transport for 127.255.255.255 49600 [TRACE] [UDP] Creating udp transport for 192.168.1.255 49600 [DEBUG] [MPMD] Discovering MPM devices on port 49600 [TRACE] [UDP] Creating udp transport for 192.168.122.255 49600 [DEBUG] [USRP1] USRP1 firmware image: /home/pari-sdr/anaconda3/share/uhd/images/usrp1_fw.ihx [INFO] [FX2] Loading firmware image: /home/pari-sdr/anaconda3/share/uhd/images/usrp1_fw.ihx... [INFO] [FX2] Firmware loaded [TRACE] [UDP] Creating udp transport for 192.168.1.255 49152 [TRACE] [UDP] Creating udp transport for 192.168.122.255 49152 [TRACE] [UDP] Creating udp transport for 192.168.1.255 49152 [TRACE] [UDP] Creating udp transport for 192.168.122.255 49152 [TRACE] [NIRIO] rpc_client connection request cancelled/aborted. [TRACE] [UDP] Creating udp transport for 192.168.1.255 49152 [TRACE] [UDP] Creating udp transport for 192.168.122.255 49152 [TRACE] [UDP] Creating udp transport for 192.168.1.255 50000 [TRACE] [UDP] Creating udp transport for 192.168.122.255 50000 [TRACE] [UHD] Device hash: 11462434024067858173 [DEBUG] [PREFS] Loaded system config file /etc/uhd/uhd.conf [DEBUG] [PREFS] Loaded user config file /home/pari-sdr/.uhd/uhd.conf [INFO] [USRP1] Opening a USRP1 device... [DEBUG] [USRP1] USRP1 FPGA image: /home/pari-sdr/anaconda3/share/uhd/images/usrp1_fpga.rbf [INFO] [FX2] Loading FPGA image: /home/pari-sdr/anaconda3/share/uhd/images/usrp1_fpga.rbf... [INFO] [FX2] FPGA image loaded [TRACE] [USRP1] poke32(13, 0x       0) [TRACE] [USRP1] poke32(14, 0x       0) [TRACE] [USRP1] peek32( 3) [TRACE] [USRP1] peek32( 3) [TRACE] [USRP1] peek32( 3) [TRACE] [USRP1] peek32( 3) [DEBUG] [USRP1] USRP1 Capabilities    number of duc's: 2    number of ddc's: 2    rx halfband:     1    tx halfband:     0 [INFO] [USRP1] Using FPGA clock rate of 64.000000MHz... [TRACE] [USRP1] codec control write reg: 0x      20 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 32  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x       0 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 0  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     106 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 262  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     280 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 640  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     380 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 896  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     400 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 1024  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     504 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 1284  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     608 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 1544  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     700 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 1792  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     800 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 2048  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     900 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 2304  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     a00 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 2560  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     b00 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 2816  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     c00 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 3072  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     d00 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 3328  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     ec0 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 3776  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     fc0 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 4032  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    10c7 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 4295  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1100 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 4352  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1249 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 4681  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1312 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 4882  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1410 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 5136  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1500 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 5376  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1600 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 5632  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1700 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 5888  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1849 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 6217  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1940 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 6464  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    2209 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 8713  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     280 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 640  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     380 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 896  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    10ff [TRACE] [USRP1] transact_spi:   slave: 2  bits: 4351  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x      20 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 32  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x       0 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 0  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     106 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 262  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     280 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 640  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     380 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 896  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     400 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 1024  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     504 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 1284  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     608 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 1544  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     700 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 1792  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     800 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 2048  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     900 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 2304  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     a00 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 2560  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     b00 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 2816  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     c00 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 3072  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     d00 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 3328  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     ec0 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 3776  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     fc0 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 4032  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    10c7 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 4295  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1100 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 4352  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1249 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 4681  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1312 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 4882  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1410 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 5136  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1500 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 5376  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1600 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 5632  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1700 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 5888  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1849 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 6217  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    1940 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 6464  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    2209 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 8713  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     280 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 640  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     380 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 896  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    10ff [TRACE] [USRP1] transact_spi:   slave: 4  bits: 4351  num_bits: 16 readback: 0 [TRACE] [USRP1] poke32(16, 0x       0) [TRACE] [USRP1] poke32(17, 0x       0) [TRACE] [USRP1] poke32(15, 0x       3) [TRACE] [USRP1] poke32(18, 0x       0) [TRACE] [USRP1] poke32(19, 0x       0) [TRACE] [USRP1] poke32(15, 0x       f) [TRACE] [USRP1] peek32( 3) [TRACE] [USRP1] peek32( 3) [TRACE] [USRP1] peek32( 3) [TRACE] [USRP1] peek32( 3) [TRACE] [USRP1] peek32( 3) [TRACE] [USRP1] peek32( 3) [TRACE] [USRP1] poke32( 6, 0xffff0000) [TRACE] [USRP1] poke32(10, 0xffff0000) [TRACE] [USRP1] poke32(23, 0x       0) [TRACE] [USRP1] poke32( 5, 0xffff0000) [TRACE] [USRP1] poke32( 9, 0xffff0000) [TRACE] [USRP1] poke32(20, 0x       0) [TRACE] [DBSRX] DBSRX: send reg 0x00, value 0x0003, start_addr = 0x0000, num_bytes 3 [TRACE] [DBSRX] DBSRX: send reg 0x01, value 0x00b6, start_addr = 0x0000, num_bytes 3 [TRACE] [DBSRX] DBSRX: send reg 0x02, value 0x003d, start_addr = 0x0000, num_bytes 3 [TRACE] [DBSRX] DBSRX: send reg 0x03, value 0x007f, start_addr = 0x0003, num_bytes 3 [TRACE] [DBSRX] DBSRX: send reg 0x04, value 0x0002, start_addr = 0x0003, num_bytes 3 [TRACE] [DBSRX] DBSRX: send reg 0x05, value 0x001f, start_addr = 0x0003, num_bytes 3 [TRACE] [DBSRX] DBSRX GC1 Gain: 0.000000 dB, dac_volts: 2.700000 V [TRACE] [USRP1] codec control write reg: 0x    24d1 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 9425  num_bits: 16 readback: 0 [TRACE] [DBSRX] DBSRX GC2 Gain: 0.000000 dB, reg: 31 [TRACE] [DBSRX] DBSRX: send reg 0x05, value 0x001f, start_addr = 0x0005, num_bytes 1 [TRACE] [USRP1] poke32(23, 0x       0) [TRACE] [USRP1] poke32( 6, 0xffff0001) [TRACE] [DBSRX] DBSRX: trying ref_clock 4000000.000000 and m_divider 4 [TRACE] [DBSRX] DBSRX R:2 [ERROR] [DBMGR] The daughterboard manager encountered a recoverable error in init. Loading the "unknown" daughterboard implementations to continue. The daughterboard cannot operate until this error is resolved. AssertionError: m and ref_clock/m >= 1e6 and ref_clock/m <= 2.5e6   in double dbsrx::set_lo_freq(double)   at /home/conda/feedstock_root/build_artifacts/uhd_1602712704625/work/host/lib/usrp/dboard/db_dbsrx.cpp:306 [TRACE] [USRP1] poke32( 6, 0xffff0000) [TRACE] [USRP1] poke32(10, 0xffff0000) [TRACE] [USRP1] poke32(23, 0x       0) [TRACE] [USRP1] poke32( 5, 0xffff0000) [TRACE] [USRP1] poke32( 9, 0xffff0000) [TRACE] [USRP1] poke32(20, 0x       0) [TRACE] [USRP1] poke32( 8, 0xffff0000) [TRACE] [USRP1] poke32(12, 0xffff0000) [TRACE] [USRP1] poke32(29, 0x       0) [TRACE] [USRP1] poke32( 7, 0xffff0000) [TRACE] [USRP1] poke32(11, 0xffff0000) [TRACE] [USRP1] poke32(26, 0x       0) [TRACE] [USRP1] codec control write reg: 0x     808 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 2056  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     808 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 2056  num_bits: 16 readback: 0 [TRACE] [USRP1] peek32( 3) [TRACE] [USRP1] peek32( 3) [TRACE] [USRP1] poke32( 1, 0x       1) [TRACE] [USRP1] poke32(33, 0x      1f) [TRACE] [USRP1] peek32( 3) [TRACE] [USRP1] peek32( 3) [TRACE] [USRP1] peek32( 3) [TRACE] [USRP1] peek32( 3) [TRACE] [USRP1] poke32( 0, 0x       1) [TRACE] [USRP1] poke32(32, 0x      1f) [TRACE] [USRP1] peek32( 3) [TRACE] [USRP1] peek32( 3) [TRACE] [USRP1] poke32(34, 0x       0) [TRACE] [USRP1] poke32(35, 0x       0) [TRACE] [USRP1] poke32(38, 0x      41) [TRACE] [USRP1] poke32(39, 0x     981)   _____________________________________________________  / |       Device: USRP1 Device |     _____________________________________________________ |    / |   |       Mboard: USRP1 |   |   serial: 45d0d3fa |   | |   |   Time sources:  none |   |   Clock sources: internal |   |   Sensors: |   |     _____________________________________________________ |   |    / |   |   |       RX DSP: 0 |   |   | |   |   |   Freq range: -32.000 to 32.000 MHz |   |     _____________________________________________________ |   |    / |   |   |       RX DSP: 1 |   |   | |   |   |   Freq range: -32.000 to 32.000 MHz |   |     _____________________________________________________ |   |    / |   |   |       RX Dboard: A |   |   |   ID: DBSRX (0x0002) |   |   |     _____________________________________________________ |   |   |    / |   |   |   |       RX Frontend: 0 |   |   |   |   Name: Unknown (0xffff) - 0 |   |   |   |   Antennas: |   |   |   |   Sensors: |   |   |   |   Freq range: 0.000 to 0.000 MHz |   |   |   |   Gain Elements: None |   |   |   |   Bandwidth range: 0.0 to 0.0 step 0.0 Hz |   |   |   |   Connection Type: IQ |   |   |   |   Uses LO offset: No |   |   |     _____________________________________________________ |   |   |    / |   |   |   |       RX Codec: A |   |   |   |   Name: ad9522 |   |   |   |   Gain range pga: 0.0 to 20.0 step 1.0 dB |   |     _____________________________________________________ |   |    / |   |   |       RX Dboard: B |   |   |     _____________________________________________________ |   |   |    / |   |   |   |       RX Frontend: 0 |   |   |   |   Name: Unknown (0xffff) - 0 |   |   |   |   Antennas: |   |   |   |   Sensors: |   |   |   |   Freq range: 0.000 to 0.000 MHz |   |   |   |   Gain Elements: None |   |   |   |   Bandwidth range: 0.0 to 0.0 step 0.0 Hz |   |   |   |   Connection Type: IQ |   |   |   |   Uses LO offset: No |   |   |     _____________________________________________________ |   |   |    / |   |   |   |       RX Codec: B |   |   |   |   Name: ad9522 |   |   |   |   Gain range pga: 0.0 to 20.0 step 1.0 dB |   |     _____________________________________________________ |   |    / |   |   |       TX DSP: 0 |   |   | |   |   |   Freq range: -44.000 to 44.000 MHz |   |     _____________________________________________________ |   |    / |   |   |       TX DSP: 1 |   |   | |   |   |   Freq range: -44.000 to 44.000 MHz |   |     _____________________________________________________ |   |    / |   |   |       TX Dboard: A |   |   |     _____________________________________________________ |   |   |    / |   |   |   |       TX Frontend: 0 |   |   |   |   Name: Unknown (0xffff) - 0 |   |   |   |   Antennas: |   |   |   |   Sensors: |   |   |   |   Freq range: 0.000 to 0.000 MHz |   |   |   |   Gain Elements: None |   |   |   |   Bandwidth range: 0.0 to 0.0 step 0.0 Hz |   |   |   |   Connection Type: IQ |   |   |   |   Uses LO offset: No |   |   |     _____________________________________________________ |   |   |    / |   |   |   |       TX Codec: A |   |   |   |   Name: ad9522 |   |   |   |   Gain range pga: -20.0 to 0.0 step 0.1 dB |   |     _____________________________________________________ |   |    / |   |   |       TX Dboard: B |   |   |     _____________________________________________________ |   |   |    / |   |   |   |       TX Frontend: 0 |   |   |   |   Name: Unknown (0xffff) - 0 |   |   |   |   Antennas: |   |   |   |   Sensors: |   |   |   |   Freq range: 0.000 to 0.000 MHz |   |   |   |   Gain Elements: None |   |   |   |   Bandwidth range: 0.0 to 0.0 step 0.0 Hz |   |   |   |   Connection Type: IQ |   |   |   |   Uses LO offset: No |   |   |     _____________________________________________________ |   |   |    / |   |   |   |       TX Codec: B |   |   |   |   Name: ad9522 |   |   |   |   Gain range pga: -20.0 to 0.0 step 0.1 dB [TRACE] [USRP1] codec control write reg: 0x     808 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 2056  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     808 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 2056  num_bits: 16 readback: 0 [TRACE] [USRP1] poke32( 6, 0xffff0000) [TRACE] [USRP1] poke32(10, 0xffff0000) [TRACE] [USRP1] poke32(23, 0x       0) [TRACE] [USRP1] poke32( 5, 0xffff0000) [TRACE] [USRP1] poke32( 9, 0xffff0000) [TRACE] [USRP1] poke32(20, 0x       0) [TRACE] [USRP1] poke32( 8, 0xffff0000) [TRACE] [USRP1] poke32(12, 0xffff0000) [TRACE] [USRP1] poke32(29, 0x       0) [TRACE] [USRP1] poke32( 7, 0xffff0000) [TRACE] [USRP1] poke32(11, 0xffff0000) [TRACE] [USRP1] poke32(26, 0x       0) [TRACE] [USRP1] codec control write reg: 0x    2400 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 9216  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    2500 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 9472  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    2600 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 9728  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    2a00 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 10752  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    2b00 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 11008  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     107 [TRACE] [USRP1] transact_spi:   slave: 2  bits: 263  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     80f [TRACE] [USRP1] transact_spi:   slave: 2  bits: 2063  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    2400 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 9216  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    2500 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 9472  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    2600 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 9728  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    2a00 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 10752  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x    2b00 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 11008  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     107 [TRACE] [USRP1] transact_spi:   slave: 4  bits: 263  num_bits: 16 readback: 0 [TRACE] [USRP1] codec control write reg: 0x     80f [TRACE] [USRP1] transact_spi:   slave: 4  bits: 2063  num_bits: 16 readback: 0 (base) [pari-sdr@dhcp-pool167 ~]$
List: usrp-users@lists.ettus.com
From: Marcus D. Leech
 
Re: [USRP-users] UHD version that supports older DBSRX on a USRP1.
Mon, Nov 16, 2020 9:20 PM
ilar construct in >> https://github.com/EttusResearch/uhd/blob/master/host/lib/usrp/dboard/db_dbsrx.cpp >> along about line 302. Am I barking up the wrong tree, or if the 'for >> (auto ....' construct needed changing in one case it needs changing >> in this case, too? I'll need to move from the conda package to the >> EPEL8 RPM package, because I know how to rebuild those and can test >> patches with those. I don't know enough c++ to be able to generate >> the patch, though. > Just in case this helps, here's logging output: > (base) [pari-sdr@dhcp-pool167 ~]$ UHD_LOG_CONSOLE_LEVEL=0 uhd_usrp_probe > [INFO] [UHD] linux; GNU C++ version 7.5.0; Boost_107400; > UHD_3.15.0.HEAD-release > [DEBUG] [MPMD] Discovering MPM devices on port 49600 > [DEBUG] [MPMD] Discovering MPM devices on port 49600 > [DEBUG] [MPMD] Discovering MPM devices on port 49600 > [TRACE] [UDP] Creating udp transport for 127.255.255.255 49600 > [TRACE] [UDP] Creating udp transport for 192.168.122.255 49600 > [TRACE] [UDP] Creating udp transport for 192.168.1.255 49600 > [DEBUG] [USRP1] USRP1 firmware image: > /home/pari-sdr/anaconda3/share/uhd/images/usrp1_fw.ihx > [TRACE] [UDP] Creating udp transport for 192.168.1.255 49152 > [TRACE] [UDP] Creating udp transport for 192.168.122.255 49152 > [TRACE] [UDP] Creating udp transport for 192.168.1.255 49152 > [TRACE] [UDP] Creating udp transport for 192.168.122.255 49152 > [TRACE] [NIRIO] rpc_client connection request cancelled/aborted. > [TRACE] [UDP] Creating udp transport for 192.168.1.255 49152 > [TRACE] [UDP] Creating udp transport for 192.168.122.255 49152 > [TRACE] [UDP] Creating udp transport for 192.168.1.255 50000 > [TRACE] [UDP] Creating udp transport for 192.168.122.255 50000 > [TRACE] [UHD] Device hash: 6433317707856818692 > [DEBUG] [PREFS] Loaded system config file /etc/uhd/uhd.conf > [DEBUG] [PREFS] Loaded user config file /home/pari-sdr/.uhd/uhd.conf > [INFO] [USRP1] Opening a USRP1 device... > [DEBUG] [USRP1] USRP1 FPGA image: > /home/pari-sdr/anaconda3/share/uhd/images/usrp1_fpga.rbf > [TRACE] [USRP1] poke32(13, 0x 0) > [TRACE] [USRP1] poke32(14, 0x 0) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] peek32( 3) > [DEBUG] [USRP1] USRP1 Capabilities number of duc's: 2 number of > ddc's: 2 rx halfband: 1 tx halfband: 0 > [INFO] [USRP1] Using FPGA clock rate of 64.000000MHz... > [TRACE] [USRP1] codec control write reg: 0x 20 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 32 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 0 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 0 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 106 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 262 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 280 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 640 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 380 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 896 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 400 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 1024 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 504 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 1284 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 608 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 1544 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 700 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 1792 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 800 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 2048 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 900 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 2304 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x a00 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 2560 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x b00 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 2816 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x c00 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 3072 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x d00 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 3328 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x ec0 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 3776 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x fc0 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 4032 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 10c7 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 4295 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1100 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 4352 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1249 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 4681 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1312 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 4882 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1410 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 5136 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1500 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 5376 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1600 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 5632 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1700 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 5888 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1849 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 6217 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1940 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 6464 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 2209 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 8713 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 280 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 640 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 380 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 896 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 10ff > [TRACE] [USRP1] transact_spi: slave: 2 bits: 4351 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 20 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 32 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 0 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 0 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 106 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 262 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 280 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 640 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 380 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 896 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 400 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 1024 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 504 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 1284 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 608 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 1544 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 700 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 1792 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 800 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 2048 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 900 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 2304 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x a00 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 2560 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x b00 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 2816 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x c00 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 3072 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x d00 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 3328 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x ec0 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 3776 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x fc0 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 4032 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 10c7 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 4295 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1100 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 4352 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1249 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 4681 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1312 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 4882 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1410 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 5136 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1500 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 5376 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1600 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 5632 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1700 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 5888 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1849 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 6217 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1940 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 6464 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 2209 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 8713 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 280 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 640 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 380 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 896 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 10ff > [TRACE] [USRP1] transact_spi: slave: 4 bits: 4351 num_bits: 16 > readback: 0 > [TRACE] [USRP1] poke32(16, 0x 0) > [TRACE] [USRP1] poke32(17, 0x 0) > [TRACE] [USRP1] poke32(15, 0x 3) > [TRACE] [USRP1] poke32(18, 0x 0) > [TRACE] [USRP1] poke32(19, 0x 0) > [TRACE] [USRP1] poke32(15, 0x f) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] poke32( 6, 0xffff0000) > [TRACE] [USRP1] poke32(10, 0xffff0000) > [TRACE] [USRP1] poke32(23, 0x 0) > [TRACE] [USRP1] poke32( 5, 0xffff0000) > [TRACE] [USRP1] poke32( 9, 0xffff0000) > [TRACE] [USRP1] poke32(20, 0x 0) > [TRACE] [DBSRX] DBSRX: send reg 0x00, value 0x0003, start_addr = > 0x0000, num_bytes 3 > [TRACE] [DBSRX] DBSRX: send reg 0x01, value 0x00b6, start_addr = > 0x0000, num_bytes 3 > [TRACE] [DBSRX] DBSRX: send reg 0x02, value 0x003d, start_addr = > 0x0000, num_bytes 3 > [TRACE] [DBSRX] DBSRX: send reg 0x03, value 0x007f, start_addr = > 0x0003, num_bytes 3 > [TRACE] [DBSRX] DBSRX: send reg 0x04, value 0x0002, start_addr = > 0x0003, num_bytes 3 > [TRACE] [DBSRX] DBSRX: send reg 0x05, value 0x001f, start_addr = > 0x0003, num_bytes 3 > [TRACE] [DBSRX] DBSRX GC1 Gain: 0.000000 dB, dac_volts: 2.700000 V > [TRACE] [USRP1] codec control write reg: 0x 24d1 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 9425 num_bits: 16 > readback: 0 > [TRACE] [DBSRX] DBSRX GC2 Gain: 0.000000 dB, reg: 31 > [TRACE] [DBSRX] DBSRX: send reg 0x05, value 0x001f, start_addr = > 0x0005, num_bytes 1 > [TRACE] [USRP1] poke32(23, 0x 0) > [TRACE] [USRP1] poke32( 6, 0xffff0001) > [TRACE] [DBSRX] DBSRX: trying ref_clock 4000000.000000 and m_divider 4 > [TRACE] [DBSRX] DBSRX R:2 > > [ERROR] [DBMGR] The daughterboard manager encountered a recoverable > error in init. > Loading the "unknown" daughterboard implementations to continue. > The daughterboard cannot operate until this error is resolved. > AssertionError: m and ref_clock/m >= 1e6 and ref_clock/m <= 2.5e6 > in double dbsrx::set_lo_freq(double) > at > /home/conda/feedstock_root/build_artifacts/uhd_1602712704625/work/host/lib/usrp/dboard/db_dbsrx.cpp:306 > > [TRACE] [USRP1] poke32( 6, 0xffff0000) > [TRACE] [USRP1] poke32(10, 0xffff0000) > [TRACE] [USRP1] poke32(23, 0x 0) > [TRACE] [USRP1] poke32( 5, 0xffff0000) > [TRACE] [USRP1] poke32( 9, 0xffff0000) > [TRACE] [USRP1] poke32(20, 0x 0) > [TRACE] [USRP1] poke32( 8, 0xffff0000) > [TRACE] [USRP1] poke32(12, 0xffff0000) > [TRACE] [USRP1] poke32(29, 0x 0) > [TRACE] [USRP1] poke32( 7, 0xffff0000) > [TRACE] [USRP1] poke32(11, 0xffff0000) > [TRACE] [USRP1] poke32(26, 0x 0) > [TRACE] [USRP1] codec control write reg: 0x 808 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 2056 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 808 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 2056 num_bits: 16 > readback: 0 > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] poke32( 1, 0x 1) > [TRACE] [USRP1] poke32(33, 0x 1f) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] poke32( 0, 0x 1) > [TRACE] [USRP1] poke32(32, 0x 1f) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] poke32(34, 0x 0) > [TRACE] [USRP1] poke32(35, 0x 0) > [TRACE] [USRP1] poke32(38, 0x 41) > [TRACE] [USRP1] poke32(39, 0x 981) > _____________________________________________________ > / > | Device: USRP1 Device > | _____________________________________________________ > | / > | | Mboard: USRP1 > | | serial: 4460cd30 > | | > | | Time sources: none > | | Clock sources: internal > | | Sensors: > | | _____________________________________________________ > | | / > | | | RX DSP: 0 > | | | > | | | Freq range: -32.000 to 32.000 MHz > | | _____________________________________________________ > | | / > | | | RX DSP: 1 > | | | > | | | Freq range: -32.000 to 32.000 MHz > | | _____________________________________________________ > | | / > | | | RX Dboard: A > | | | ID: DBSRX (0x0002) > | | | _____________________________________________________ > | | | / > | | | | RX Frontend: 0 > | | | | Name: Unknown (0xffff) - 0 > | | | | Antennas: > | | | | Sensors: > | | | | Freq range: 0.000 to 0.000 MHz > | | | | Gain Elements: None > | | | | Bandwidth range: 0.0 to 0.0 step 0.0 Hz > | | | | Connection Type: IQ > | | | | Uses LO offset: No > | | | _____________________________________________________ > | | | / > | | | | RX Codec: A > | | | | Name: ad9522 > | | | | Gain range pga: 0.0 to 20.0 step 1.0 dB > | | _____________________________________________________ > | | / > | | | RX Dboard: B > | | | _____________________________________________________ > | | | / > | | | | RX Frontend: 0 > | | | | Name: Unknown (0xffff) - 0 > | | | | Antennas: > | | | | Sensors: > | | | | Freq range: 0.000 to 0.000 MHz > | | | | Gain Elements: None > | | | | Bandwidth range: 0.0 to 0.0 step 0.0 Hz > | | | | Connection Type: IQ > | | | | Uses LO offset: No > | | | _____________________________________________________ > | | | / > | | | | RX Codec: B > | | | | Name: ad9522 > | | | | Gain range pga: 0.0 to 20.0 step 1.0 dB > | | _____________________________________________________ > | | / > | | | TX DSP: 0 > | | | > | | | Freq range: -44.000 to 44.000 MHz > | | _____________________________________________________ > | | / > | | | TX DSP: 1 > | | | > | | | Freq range: -44.000 to 44.000 MHz > | | _____________________________________________________ > | | / > | | | TX Dboard: A > | | | _____________________________________________________ > | | | / > | | | | TX Frontend: 0 > | | | | Name: Unknown (0xffff) - 0 > | | | | Antennas: > | | | | Sensors: > | | | | Freq range: 0.000 to 0.000 MHz > | | | | Gain Elements: None > | | | | Bandwidth range: 0.0 to 0.0 step 0.0 Hz > | | | | Connection Type: IQ > | | | | Uses LO offset: No > | | | _____________________________________________________ > | | | / > | | | | TX Codec: A > | | | | Name: ad9522 > | | | | Gain range pga: -20.0 to 0.0 step 0.1 dB > | | _____________________________________________________ > | | / > | | | TX Dboard: B > | | | _____________________________________________________ > | | | / > | | | | TX Frontend: 0 > | | | | Name: Unknown (0xffff) - 0 > | | | | Antennas: > | | | | Sensors: > | | | | Freq range: 0.000 to 0.000 MHz > | | | | Gain Elements: None > | | | | Bandwidth range: 0.0 to 0.0 step 0.0 Hz > | | | | Connection Type: IQ > | | | | Uses LO offset: No > | | | _____________________________________________________ > | | | / > | | | | TX Codec: B > | | | | Name: ad9522 > | | | | Gain range pga: -20.0 to 0.0 step 0.1 dB > > [TRACE] [USRP1] codec control write reg: 0x 808 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 2056 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 808 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 2056 num_bits: 16 > readback: 0 > [TRACE] [USRP1] poke32( 6, 0xffff0000) > [TRACE] [USRP1] poke32(10, 0xffff0000) > [TRACE] [USRP1] poke32(23, 0x 0) > [TRACE] [USRP1] poke32( 5, 0xffff0000) > [TRACE] [USRP1] poke32( 9, 0xffff0000) > [TRACE] [USRP1] poke32(20, 0x 0) > [TRACE] [USRP1] poke32( 8, 0xffff0000) > [TRACE] [USRP1] poke32(12, 0xffff0000) > [TRACE] [USRP1] poke32(29, 0x 0) > [TRACE] [USRP1] poke32( 7, 0xffff0000) > [TRACE] [USRP1] poke32(11, 0xffff0000) > [TRACE] [USRP1] poke32(26, 0x 0) > [TRACE] [USRP1] codec control write reg: 0x 2400 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 9216 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 2500 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 9472 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 2600 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 9728 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 2a00 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 10752 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 2b00 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 11008 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 107 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 263 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 80f > [TRACE] [USRP1] transact_spi: slave: 2 bits: 2063 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 2400 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 9216 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 2500 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 9472 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 2600 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 9728 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 2a00 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 10752 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 2b00 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 11008 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 107 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 263 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 80f > [TRACE] [USRP1] transact_spi: slave: 4 bits: 2063 num_bits: 16 > readback: 0 > (base) [pari-sdr@dhcp-pool167 ~]$ > > And with a second USRP1: > (base) [pari-sdr@dhcp-pool167 ~]$ UHD_LOG_CONSOLE_LEVEL=0 uhd_usrp_probe > [INFO] [UHD] linux; GNU C++ version 7.5.0; Boost_107400; > UHD_3.15.0.HEAD-release > [DEBUG] [MPMD] Discovering MPM devices on port 49600 > [DEBUG] [MPMD] Discovering MPM devices on port 49600 > [TRACE] [UDP] Creating udp transport for 127.255.255.255 49600 > [TRACE] [UDP] Creating udp transport for 192.168.1.255 49600 > [DEBUG] [MPMD] Discovering MPM devices on port 49600 > [TRACE] [UDP] Creating udp transport for 192.168.122.255 49600 > [DEBUG] [USRP1] USRP1 firmware image: > /home/pari-sdr/anaconda3/share/uhd/images/usrp1_fw.ihx > [INFO] [FX2] Loading firmware image: > /home/pari-sdr/anaconda3/share/uhd/images/usrp1_fw.ihx... > [INFO] [FX2] Firmware loaded > [TRACE] [UDP] Creating udp transport for 192.168.1.255 49152 > [TRACE] [UDP] Creating udp transport for 192.168.122.255 49152 > [TRACE] [UDP] Creating udp transport for 192.168.1.255 49152 > [TRACE] [UDP] Creating udp transport for 192.168.122.255 49152 > [TRACE] [NIRIO] rpc_client connection request cancelled/aborted. > [TRACE] [UDP] Creating udp transport for 192.168.1.255 49152 > [TRACE] [UDP] Creating udp transport for 192.168.122.255 49152 > [TRACE] [UDP] Creating udp transport for 192.168.1.255 50000 > [TRACE] [UDP] Creating udp transport for 192.168.122.255 50000 > [TRACE] [UHD] Device hash: 11462434024067858173 > [DEBUG] [PREFS] Loaded system config file /etc/uhd/uhd.conf > [DEBUG] [PREFS] Loaded user config file /home/pari-sdr/.uhd/uhd.conf > [INFO] [USRP1] Opening a USRP1 device... > [DEBUG] [USRP1] USRP1 FPGA image: > /home/pari-sdr/anaconda3/share/uhd/images/usrp1_fpga.rbf > [INFO] [FX2] Loading FPGA image: > /home/pari-sdr/anaconda3/share/uhd/images/usrp1_fpga.rbf... > [INFO] [FX2] FPGA image loaded > [TRACE] [USRP1] poke32(13, 0x 0) > [TRACE] [USRP1] poke32(14, 0x 0) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] peek32( 3) > [DEBUG] [USRP1] USRP1 Capabilities number of duc's: 2 number of > ddc's: 2 rx halfband: 1 tx halfband: 0 > [INFO] [USRP1] Using FPGA clock rate of 64.000000MHz... > [TRACE] [USRP1] codec control write reg: 0x 20 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 32 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 0 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 0 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 106 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 262 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 280 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 640 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 380 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 896 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 400 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 1024 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 504 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 1284 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 608 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 1544 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 700 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 1792 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 800 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 2048 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 900 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 2304 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x a00 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 2560 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x b00 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 2816 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x c00 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 3072 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x d00 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 3328 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x ec0 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 3776 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x fc0 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 4032 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 10c7 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 4295 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1100 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 4352 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1249 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 4681 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1312 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 4882 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1410 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 5136 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1500 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 5376 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1600 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 5632 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1700 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 5888 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1849 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 6217 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1940 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 6464 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 2209 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 8713 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 280 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 640 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 380 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 896 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 10ff > [TRACE] [USRP1] transact_spi: slave: 2 bits: 4351 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 20 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 32 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 0 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 0 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 106 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 262 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 280 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 640 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 380 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 896 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 400 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 1024 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 504 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 1284 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 608 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 1544 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 700 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 1792 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 800 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 2048 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 900 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 2304 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x a00 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 2560 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x b00 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 2816 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x c00 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 3072 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x d00 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 3328 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x ec0 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 3776 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x fc0 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 4032 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 10c7 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 4295 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1100 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 4352 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1249 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 4681 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1312 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 4882 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1410 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 5136 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1500 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 5376 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1600 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 5632 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1700 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 5888 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1849 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 6217 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 1940 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 6464 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 2209 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 8713 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 280 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 640 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 380 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 896 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 10ff > [TRACE] [USRP1] transact_spi: slave: 4 bits: 4351 num_bits: 16 > readback: 0 > [TRACE] [USRP1] poke32(16, 0x 0) > [TRACE] [USRP1] poke32(17, 0x 0) > [TRACE] [USRP1] poke32(15, 0x 3) > [TRACE] [USRP1] poke32(18, 0x 0) > [TRACE] [USRP1] poke32(19, 0x 0) > [TRACE] [USRP1] poke32(15, 0x f) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] poke32( 6, 0xffff0000) > [TRACE] [USRP1] poke32(10, 0xffff0000) > [TRACE] [USRP1] poke32(23, 0x 0) > [TRACE] [USRP1] poke32( 5, 0xffff0000) > [TRACE] [USRP1] poke32( 9, 0xffff0000) > [TRACE] [USRP1] poke32(20, 0x 0) > [TRACE] [DBSRX] DBSRX: send reg 0x00, value 0x0003, start_addr = > 0x0000, num_bytes 3 > [TRACE] [DBSRX] DBSRX: send reg 0x01, value 0x00b6, start_addr = > 0x0000, num_bytes 3 > [TRACE] [DBSRX] DBSRX: send reg 0x02, value 0x003d, start_addr = > 0x0000, num_bytes 3 > [TRACE] [DBSRX] DBSRX: send reg 0x03, value 0x007f, start_addr = > 0x0003, num_bytes 3 > [TRACE] [DBSRX] DBSRX: send reg 0x04, value 0x0002, start_addr = > 0x0003, num_bytes 3 > [TRACE] [DBSRX] DBSRX: send reg 0x05, value 0x001f, start_addr = > 0x0003, num_bytes 3 > [TRACE] [DBSRX] DBSRX GC1 Gain: 0.000000 dB, dac_volts: 2.700000 V > [TRACE] [USRP1] codec control write reg: 0x 24d1 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 9425 num_bits: 16 > readback: 0 > [TRACE] [DBSRX] DBSRX GC2 Gain: 0.000000 dB, reg: 31 > [TRACE] [DBSRX] DBSRX: send reg 0x05, value 0x001f, start_addr = > 0x0005, num_bytes 1 > [TRACE] [USRP1] poke32(23, 0x 0) > [TRACE] [USRP1] poke32( 6, 0xffff0001) > [TRACE] [DBSRX] DBSRX: trying ref_clock 4000000.000000 and m_divider 4 > [TRACE] [DBSRX] DBSRX R:2 > > [ERROR] [DBMGR] The daughterboard manager encountered a recoverable > error in init. > Loading the "unknown" daughterboard implementations to continue. > The daughterboard cannot operate until this error is resolved. > AssertionError: m and ref_clock/m >= 1e6 and ref_clock/m <= 2.5e6 > in double dbsrx::set_lo_freq(double) > at > /home/conda/feedstock_root/build_artifacts/uhd_1602712704625/work/host/lib/usrp/dboard/db_dbsrx.cpp:306 > > [TRACE] [USRP1] poke32( 6, 0xffff0000) > [TRACE] [USRP1] poke32(10, 0xffff0000) > [TRACE] [USRP1] poke32(23, 0x 0) > [TRACE] [USRP1] poke32( 5, 0xffff0000) > [TRACE] [USRP1] poke32( 9, 0xffff0000) > [TRACE] [USRP1] poke32(20, 0x 0) > [TRACE] [USRP1] poke32( 8, 0xffff0000) > [TRACE] [USRP1] poke32(12, 0xffff0000) > [TRACE] [USRP1] poke32(29, 0x 0) > [TRACE] [USRP1] poke32( 7, 0xffff0000) > [TRACE] [USRP1] poke32(11, 0xffff0000) > [TRACE] [USRP1] poke32(26, 0x 0) > [TRACE] [USRP1] codec control write reg: 0x 808 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 2056 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 808 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 2056 num_bits: 16 > readback: 0 > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] poke32( 1, 0x 1) > [TRACE] [USRP1] poke32(33, 0x 1f) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] poke32( 0, 0x 1) > [TRACE] [USRP1] poke32(32, 0x 1f) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] poke32(34, 0x 0) > [TRACE] [USRP1] poke32(35, 0x 0) > [TRACE] [USRP1] poke32(38, 0x 41) > [TRACE] [USRP1] poke32(39, 0x 981) > _____________________________________________________ > / > | Device: USRP1 Device > | _____________________________________________________ > | / > | | Mboard: USRP1 > | | serial: 45d0d3fa > | | > | | Time sources: none > | | Clock sources: internal > | | Sensors: > | | _____________________________________________________ > | | / > | | | RX DSP: 0 > | | | > | | | Freq range: -32.000 to 32.000 MHz > | | _____________________________________________________ > | | / > | | | RX DSP: 1 > | | | > | | | Freq range: -32.000 to 32.000 MHz > | | _____________________________________________________ > | | / > | | | RX Dboard: A > | | | ID: DBSRX (0x0002) > | | | _____________________________________________________ > | | | / > | | | | RX Frontend: 0 > | | | | Name: Unknown (0xffff) - 0 > | | | | Antennas: > | | | | Sensors: > | | | | Freq range: 0.000 to 0.000 MHz > | | | | Gain Elements: None > | | | | Bandwidth range: 0.0 to 0.0 step 0.0 Hz > | | | | Connection Type: IQ > | | | | Uses LO offset: No > | | | _____________________________________________________ > | | | / > | | | | RX Codec: A > | | | | Name: ad9522 > | | | | Gain range pga: 0.0 to 20.0 step 1.0 dB > | | _____________________________________________________ > | | / > | | | RX Dboard: B > | | | _____________________________________________________ > | | | / > | | | | RX Frontend: 0 > | | | | Name: Unknown (0xffff) - 0 > | | | | Antennas: > | | | | Sensors: > | | | | Freq range: 0.000 to 0.000 MHz > | | | | Gain Elements: None > | | | | Bandwidth range: 0.0 to 0.0 step 0.0 Hz > | | | | Connection Type: IQ > | | | | Uses LO offset: No > | | | _____________________________________________________ > | | | / > | | | | RX Codec: B > | | | | Name: ad9522 > | | | | Gain range pga: 0.0 to 20.0 step 1.0 dB > | | _____________________________________________________ > | | / > | | | TX DSP: 0 > | | | > | | | Freq range: -44.000 to 44.000 MHz > | | _____________________________________________________ > | | / > | | | TX DSP: 1 > | | | > | | | Freq range: -44.000 to 44.000 MHz > | | _____________________________________________________ > | | / > | | | TX Dboard: A > | | | _____________________________________________________ > | | | / > | | | | TX Frontend: 0 > | | | | Name: Unknown (0xffff) - 0 > | | | | Antennas: > | | | | Sensors: > | | | | Freq range: 0.000 to 0.000 MHz > | | | | Gain Elements: None > | | | | Bandwidth range: 0.0 to 0.0 step 0.0 Hz > | | | | Connection Type: IQ > | | | | Uses LO offset: No > | | | _____________________________________________________ > | | | / > | | | | TX Codec: A > | | | | Name: ad9522 > | | | | Gain range pga: -20.0 to 0.0 step 0.1 dB > | | _____________________________________________________ > | | / > | | | TX Dboard: B > | | | _____________________________________________________ > | | | / > | | | | TX Frontend: 0 > | | | | Name: Unknown (0xffff) - 0 > | | | | Antennas: > | | | | Sensors: > | | | | Freq range: 0.000 to 0.000 MHz > | | | | Gain Elements: None > | | | | Bandwidth range: 0.0 to 0.0 step 0.0 Hz > | | | | Connection Type: IQ > | | | | Uses LO offset: No > | | | _____________________________________________________ > | | | / > | | | | TX Codec: B > | | | | Name: ad9522 > | | | | Gain range pga: -20.0 to 0.0 step 0.1 dB > > [TRACE] [USRP1] codec control write reg: 0x 808 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 2056 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 808 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 2056 num_bits: 16 > readback: 0 > [TRACE] [USRP1] poke32( 6, 0xffff0000) > [TRACE] [USRP1] poke32(10, 0xffff0000) > [TRACE] [USRP1] poke32(23, 0x 0) > [TRACE] [USRP1] poke32( 5, 0xffff0000) > [TRACE] [USRP1] poke32( 9, 0xffff0000) > [TRACE] [USRP1] poke32(20, 0x 0) > [TRACE] [USRP1] poke32( 8, 0xffff0000) > [TRACE] [USRP1] poke32(12, 0xffff0000) > [TRACE] [USRP1] poke32(29, 0x 0) > [TRACE] [USRP1] poke32( 7, 0xffff0000) > [TRACE] [USRP1] poke32(11, 0xffff0000) > [TRACE] [USRP1] poke32(26, 0x 0) > [TRACE] [USRP1] codec control write reg: 0x 2400 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 9216 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 2500 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 9472 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 2600 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 9728 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 2a00 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 10752 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 2b00 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 11008 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 107 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 263 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 80f > [TRACE] [USRP1] transact_spi: slave: 2 bits: 2063 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 2400 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 9216 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 2500 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 9472 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 2600 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 9728 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 2a00 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 10752 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 2b00 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 11008 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 107 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 263 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 80f > [TRACE] [USRP1] transact_spi: slave: 4 bits: 2063 num_bits: 16 > readback: 0 > (base) [pari-sdr@dhcp-pool167 ~]$ > > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com I'll note that there was a fair amount of churn between UHD 3.15 and UHD 4.0 on dbs_rx -- whether that fixes this issue or not is another matter.
List: usrp-users@lists.ettus.com
From: Marcus D. Leech
 
Re: [USRP-users] UHD version that supports older DBSRX on a USRP1.
Mon, Nov 16, 2020 10:26 PM
this error is resolved. > AssertionError: m and ref_clock/m >= 1e6 and ref_clock/m <= 2.5e6 > in double dbsrx::set_lo_freq(double) > at > /home/conda/feedstock_root/build_artifacts/uhd_1602712704625/work/host/lib/usrp/dboard/db_dbsrx.cpp:306 If you look at the context of this assertion--it should never be asserted. ref_clock is 4e6 and m is 4, so the test is satisfied, and therefore the assertion shouldn't fail. I wonder if this is a compiler issue, or an issue with the UHD_ASSERT logic? > > [TRACE] [USRP1] poke32( 6, 0xffff0000) > [TRACE] [USRP1] poke32(10, 0xffff0000) > [TRACE] [USRP1] poke32(23, 0x 0) > [TRACE] [USRP1] poke32( 5, 0xffff0000) > [TRACE] [USRP1] poke32( 9, 0xffff0000) > [TRACE] [USRP1] poke32(20, 0x 0) > [TRACE] [USRP1] poke32( 8, 0xffff0000) > [TRACE] [USRP1] poke32(12, 0xffff0000) > [TRACE] [USRP1] poke32(29, 0x 0) > [TRACE] [USRP1] poke32( 7, 0xffff0000) > [TRACE] [USRP1] poke32(11, 0xffff0000) > [TRACE] [USRP1] poke32(26, 0x 0) > [TRACE] [USRP1] codec control write reg: 0x 808 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 2056 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 808 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 2056 num_bits: 16 > readback: 0 > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] poke32( 1, 0x 1) > [TRACE] [USRP1] poke32(33, 0x 1f) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] poke32( 0, 0x 1) > [TRACE] [USRP1] poke32(32, 0x 1f) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] peek32( 3) > [TRACE] [USRP1] poke32(34, 0x 0) > [TRACE] [USRP1] poke32(35, 0x 0) > [TRACE] [USRP1] poke32(38, 0x 41) > [TRACE] [USRP1] poke32(39, 0x 981) > _____________________________________________________ > / > | Device: USRP1 Device > | _____________________________________________________ > | / > | | Mboard: USRP1 > | | serial: 45d0d3fa > | | > | | Time sources: none > | | Clock sources: internal > | | Sensors: > | | _____________________________________________________ > | | / > | | | RX DSP: 0 > | | | > | | | Freq range: -32.000 to 32.000 MHz > | | _____________________________________________________ > | | / > | | | RX DSP: 1 > | | | > | | | Freq range: -32.000 to 32.000 MHz > | | _____________________________________________________ > | | / > | | | RX Dboard: A > | | | ID: DBSRX (0x0002) > | | | _____________________________________________________ > | | | / > | | | | RX Frontend: 0 > | | | | Name: Unknown (0xffff) - 0 > | | | | Antennas: > | | | | Sensors: > | | | | Freq range: 0.000 to 0.000 MHz > | | | | Gain Elements: None > | | | | Bandwidth range: 0.0 to 0.0 step 0.0 Hz > | | | | Connection Type: IQ > | | | | Uses LO offset: No > | | | _____________________________________________________ > | | | / > | | | | RX Codec: A > | | | | Name: ad9522 > | | | | Gain range pga: 0.0 to 20.0 step 1.0 dB > | | _____________________________________________________ > | | / > | | | RX Dboard: B > | | | _____________________________________________________ > | | | / > | | | | RX Frontend: 0 > | | | | Name: Unknown (0xffff) - 0 > | | | | Antennas: > | | | | Sensors: > | | | | Freq range: 0.000 to 0.000 MHz > | | | | Gain Elements: None > | | | | Bandwidth range: 0.0 to 0.0 step 0.0 Hz > | | | | Connection Type: IQ > | | | | Uses LO offset: No > | | | _____________________________________________________ > | | | / > | | | | RX Codec: B > | | | | Name: ad9522 > | | | | Gain range pga: 0.0 to 20.0 step 1.0 dB > | | _____________________________________________________ > | | / > | | | TX DSP: 0 > | | | > | | | Freq range: -44.000 to 44.000 MHz > | | _____________________________________________________ > | | / > | | | TX DSP: 1 > | | | > | | | Freq range: -44.000 to 44.000 MHz > | | _____________________________________________________ > | | / > | | | TX Dboard: A > | | | _____________________________________________________ > | | | / > | | | | TX Frontend: 0 > | | | | Name: Unknown (0xffff) - 0 > | | | | Antennas: > | | | | Sensors: > | | | | Freq range: 0.000 to 0.000 MHz > | | | | Gain Elements: None > | | | | Bandwidth range: 0.0 to 0.0 step 0.0 Hz > | | | | Connection Type: IQ > | | | | Uses LO offset: No > | | | _____________________________________________________ > | | | / > | | | | TX Codec: A > | | | | Name: ad9522 > | | | | Gain range pga: -20.0 to 0.0 step 0.1 dB > | | _____________________________________________________ > | | / > | | | TX Dboard: B > | | | _____________________________________________________ > | | | / > | | | | TX Frontend: 0 > | | | | Name: Unknown (0xffff) - 0 > | | | | Antennas: > | | | | Sensors: > | | | | Freq range: 0.000 to 0.000 MHz > | | | | Gain Elements: None > | | | | Bandwidth range: 0.0 to 0.0 step 0.0 Hz > | | | | Connection Type: IQ > | | | | Uses LO offset: No > | | | _____________________________________________________ > | | | / > | | | | TX Codec: B > | | | | Name: ad9522 > | | | | Gain range pga: -20.0 to 0.0 step 0.1 dB > > [TRACE] [USRP1] codec control write reg: 0x 808 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 2056 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 808 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 2056 num_bits: 16 > readback: 0 > [TRACE] [USRP1] poke32( 6, 0xffff0000) > [TRACE] [USRP1] poke32(10, 0xffff0000) > [TRACE] [USRP1] poke32(23, 0x 0) > https://www.amazon.ca/Breakout-Connector-Female-Adapter-Terminal/dp/B07DL13B32/ref=sr_1_23_sspa?dchild=1&gclid=Cj0KCQiA48j9BRC-ARIsAMQu3WS6mqz1QoEYjrHj2vHgONo0eOz7jWLd7vf1879y7aTpPzTauZuEmF8aAvu5EALw_wcB&hvadid=208320688227&hvdev=c&hvlocphy=9000707&hvnetw=g&hvqmt=e&hvrand=9845139346444461649&hvtargid=kwd-301399804745&hydadcr=1500_9454465&keywords=usb+to+rs-232&qid=1605565159&sr=8-23-spons&tag=googcana-20&psc=1&spLa=ZW5jcnlwdGVkUXVhbGlmaWVyPUE3N1BFTEhCQjBFVzImZW5jcnlwdGVkSWQ9QTAxODU5NjgyU0NJT0EwRUFXTllZJmVuY3J5cHRlZEFkSWQ9QTAzMTcwMTUxSDdXTFpLRERMR1BJJndpZGdldE5hbWU9c3BfbXRmJmFjdGlvbj1jbGlja1JlZGlyZWN0JmRvTm90TG9nQ2xpY2s9dHJ1ZQ== > [TRACE] [USRP1] poke32( 5, 0xffff0000) > [TRACE] [USRP1] poke32( 9, 0xffff0000) > [TRACE] [USRP1] poke32(20, 0x 0) > [TRACE] [USRP1] poke32( 8, 0xffff0000) > [TRACE] [USRP1] poke32(12, 0xffff0000) > [TRACE] [USRP1] poke32(29, 0x 0) > [TRACE] [USRP1] poke32( 7, 0xffff0000) > [TRACE] [USRP1] poke32(11, 0xffff0000) > [TRACE] [USRP1] poke32(26, 0x 0) > [TRACE] [USRP1] codec control write reg: 0x 2400 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 9216 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 2500 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 9472 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 2600 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 9728 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 2a00 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 10752 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 2b00 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 11008 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 107 > [TRACE] [USRP1] transact_spi: slave: 2 bits: 263 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 80f > [TRACE] [USRP1] transact_spi: slave: 2 bits: 2063 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 2400 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 9216 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 2500 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 9472 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 2600 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 9728 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 2a00 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 10752 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 2b00 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 11008 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 107 > [TRACE] [USRP1] transact_spi: slave: 4 bits: 263 num_bits: 16 > readback: 0 > [TRACE] [USRP1] codec control write reg: 0x 80f > [TRACE] [USRP1] transact_spi: slave: 4 bits: 2063 num_bits: 16 > readback: 0 > (base) [pari-sdr@dhcp-pool167 ~]$ > > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
List: tacomaart@list.cityoftacoma.org
From: Paul Uhl
 
Come to LADYFEST 2009 and support your local female artists!
Mon, Jun 1, 2009 4:27 AM
List: tacomaart@list.cityoftacoma.org
From: Lacey Leffler
 
You Could Win $25,000 in 17 days and support the arts
Wed, Jun 9, 2010 10:33 PM
me at 505 Broadway or a guaranteed minimum of $25,000 up to $600,000*, depending upon the total final ticket sales. 1st Prize: A three-year lease on a Toyota Prius thanks to Jim "The Golfer" and Kay Love at Titus Will Toyota OR $7,500 cash 2nd Prize: A luxurious cruise for two to anywhere Holland America Tours OR $5,000 cash 3rd Prize: A seven-night stay in Bali, Indonesia OR $1,500 cash 4th Prize: A final prize of $1,000 To date, there are about 3,600 tickets sold. The odds of winning one of the remaining amazing prizes is very good! Tickets are available for purchase by calling 1.877.622.4511. * See complete rules and regulations at www.tacomaraffle.org
List: pjsip@lists.pjsip.org
From: Yuming Zheng
 
rfc 6236 Negotiation of Generic Image Attributes in the SDP support.
Fri, Sep 28, 2012 3:00 AM
List: members@lists.national-coalition-literacy.org
From: Sharon Bonney
 
FREE COABE Webinar to support NCL's AEFL Campaign
Sat, Jul 16, 2016 4:29 PM
List: pjsip@lists.pjsip.org
From: Benny Prijono
 
Re: [pjsip] FW: Intergrating Answering Fax Tone Detection support
Sun, Oct 21, 2007 10:57 AM
> b) put_frame () --> This will save to PCM frames to a buffer but these PCM > frames will come from Sound Port i.e. MIC. > > This is my understanding, please correct me if I am wrong on this. > > My requirement is to detect > > a) Answering Fax Machine detection --> which can be done by scanning > incoming Frames after they have been decoded in stream.c > > b) Answering Machine detection --> This should be done only when 200 OK > has been received from other side. Is there any way to handle from > application, to enable Media port only when 200 Ok has been received. The easiest is to implement a sink media port (like WAV capture), thus implementing put_frame(). Then you connect the call's stream to this media port, in the conference bridge, and at the same time you also connect the call's stream to the sound device as usual. You can control when exactly you want to connect them, as this is done in application's code. The drawback of this approach is you won't be able to remove the tone signal from the stream's signal, since connection from stream to sound device is independent from the connection from stream to your tone detection port. Another approach is to implement "dual-sided" media port. A put_frame() on the upstream side will trigger put_frame() to be called on the downstream side, and a get_frame() on the upstream side will also trigger get_frame() on the downstream side. The resample port is implemented this way, have a look at resample_port.c for the details. Then you can "insert" your tone detection media port between the call's stream and the bridge. You'll need to modify pjsua-lib code to do this since this kind of interconnection currently cannot be done at application's code. regards, -benny > Regards, > Ravi Inder Singh.
List: pjsip@lists.pjsip.org
From: Benny Prijono
 
Re: [pjsip] FW: Intergrating Answering Fax Tone Detection support
Fri, Oct 26, 2007 6:54 AM
ection --> this should be done only when 200 OK > has been received from other side. Is there any way to handle from > Application, to enable Media port only when 200 Ok has been received. --> > Reply waited not given last time also. Doesn't pjsua_call_info give you anything you need for this? -benny > > > Thanks in advance > Regards, > Ravi Inder Singh
Next page
Empathy v1.0   2026 ©emwd.com
Documentation