Hi,
Guest
Search results for all lists
List: time-nuts@lists.febo.com
From: Eric Haskell
Link to Frequency Electronics Precision Frequency Generation Tutorial PDF
Tue, Aug 11, 2009 4:29 AM
I found this link on the Long Island IEEE MTT website and thought others may
want a look:
http://www.ieee.li/pdf/viewgraphs/precision_frequency_generation.pdf
-Eric Haskell
List: ctbirds@lists.ctbirding.org
From: Julian Hough
West Haven Thayer's pix and more..
Mon, Apr 20, 2015 3:49 AM
See at:
https://naturescapeimages.wordpress.com/2015/04/20/gulls-gone-wild/
Julian Hough
CT, 06519
USA
jrhough1@snet.net
Blog: www.naturescapeimages.wordpress.com
website: www.JulianRHough.com
List: ctbirds@lists.ctbirding.org
From: Anthony Zemba
What time does COA meeting start tomorrow?
Sat, Mar 24, 2018 1:50 AM
I did not see it posted on the website
Sent from my iPad
List: great-loop@lists.trawlering.com
From: John & Judy Gill
LOCKING THROUGH” & An ERIE CANAL CRUISE
Sat, Apr 28, 2012 7:25 PM
John and Judy Gill of the Two J’s V are pleased to announce a new section to their popular Great Loop website for: POWER POINT PRESENTATIONS. Actually the website presentations are in a “MOVIE” format, so that viewers / presenters do not need to have Power Point software to view and/or run these presentations.
List: tacomaart@list.cityoftacoma.org
From: Giselle Lorenz Brock
June 11th News - Sound Movement Arts Center
Fri, Jun 10, 2016 6:58 AM
u=24a75b420ea59dad922b1af39&id=774acb2a59&e=3c501da8c4>
[image: Website]
Website
[image: Email]
Email
List: usrp-users@lists.ettus.com
From: Wade Fife
Re: Error when synthesizing example OOT block : IP "cmplx_mul" is locked
Fri, Feb 3, 2023 7:27 PM
/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xml'
>
> CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file
> '/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xml'
>
> CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file
> '/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xml'
>
> [
List: usrp-users@lists.ettus.com
From: Minutolo, Lorenzo
Re: Error when synthesizing example OOT block : IP "cmplx_mul" is locked
Fri, Feb 3, 2023 6:48 PM
List: usrp-users@lists.ettus.com
From: Bachmaier, Luca
Re: RFNoC Image Builder: two problems with Vitis HLS
Thu, Jul 13, 2023 1:33 PM
BOM file '/home/fobp/sdr/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/axi_hb31/axi_hb31.xml'
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/home/fobp/sdr/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/axi_hb31/axi_hb31.xml'
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/home/fobp/sdr/uhd/fpga/usrp3/top/n3xx/build-ip
List: usrp-users@lists.ettus.com
From: Rob Kossler
Re: [USRP-users] rfnoc build standard image x310 failing
Thu, May 21, 2020 6:33 PM
.
>
>
>
>
>
> I installed vivado 2017.4 with uhd 3.14.1.1 and get this error:
>
>
>
> BUILDER: Releasing IP location:
> /home/nvd/rfnoc/src/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/aurora_64b66b_pcs_pma
>
> Using parser configuration from:
> /home/nvd/rfnoc/src/uhd/fpga-src/usrp3/top/x300/dev_config.json
>
> [00:00:00] Executing command: vivado -
List: usrp-users@lists.ettus.com
From: Jeff Scaparra
Re: [USRP-users] FPGA reprogramming and real-time
Mon, Oct 10, 2011 5:55 PM
Process "Map" failed
INFO:TclTasksC:1850 - process run : Generate Programming File is done.
touch /home/scap/Radio/uhd/fpga/usrp2/top/N2x0/build-N200R3/u2plus.bin
python /home/scap/Radio/uhd/fpga/usrp2/top/python/check_timing.py
/home/scap/Radio/uhd/fpga/usrp2/top/N2x0/build-N200R3/u2plus.twr
Traceback (most recent call last):
File "/home/scap/Radio/uhd/fpga