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List: discuss@lists.openscad.org
From: jazzjohn
 
hull() issue? (or is it me?)
Thu, Jun 15, 2017 5:24 PM
{ front(500); translate([3000,-600,0]) back(250); translate([3000,600,0]) back(250); } //hull() //When uncommented, hull misses the back() objects called in top() and bottom()
List: usrp-users@lists.ettus.com
From: Matt Ettus
 
Re: [USRP-users] How to build USRP2 binary for BASIC RX/TX from scratch
Tue, Mar 15, 2011 6:36 AM
I need to know > which is the top levelmakefile which builds the entire project OR > perhaps a bunch of makefilesthat build parts of it. Also the process of > going from the coed to the files to be burned on the SD. I do have > xilinx ISE12.4. The usrp2/top/u2_rev3 directory has the top level makefile you need.
List: time-nuts@lists.febo.com
From: Stewart Bryant
 
Re: [time-nuts] Subject: Listening to the List Owner
Wed, Sep 21, 2011 12:31 PM
. > > Microsoft (Exchange), RIM (Blackberry), and Google (Android), all make > it difficult-to-impossible to _not_ top post. But they're all clueless > net newbies, too. If you look at the IETF lists (where you will find a high proportion of clueful net oldies) you will see that top posting is at least as common, if not more common, than bottom posting.
List: discuss@lists.openscad.org
From: Jordan Brown
 
Re: Going to delete account and try again
Mon, Sep 5, 2022 1:40 AM
https://lists.openscad.org/empathy/thread/HV5QQR27S54WQ5X2VMXFGRW7HBP7WAGD In fact, I don't know how you got your e-mail messages to have your real name at the top.
List: discuss@lists.openscad.org
From: Lenore Horner
 
Re: export to svg
Sun, Mar 19, 2023 11:58 AM
That complained that there was not top level geometry. So I tried linear_extrude on to thicken the whole geometry to 1 and then projecting that. Now I'm back to the complaint that the top level object is no at 3D object and a refusal to export an stl file. I tried this in the same two versions as before. Lenore
List: usrp-users@lists.ettus.com
From: perper@o2.pl
 
Re: X410 FPGA build failure with UHD-4.4
Fri, Aug 25, 2023 2:52 PM
-verilog_define RFNOC_IMAGE_CORE_HDR=x410_200_rfnoc_image_core.vh -verilog_define UHD_FPGA_DIR=/home/user/RFSoC/uhd/fpga/usrp3/top/../.
List: usrp-users@lists.ettus.com
From: Mark McCarron
 
Re: [USRP-users] USRP B100 Tuning Issue
Wed, May 8, 2013 12:54 AM
I've often used this website to help me design filters from parts I happened to have lying around: http://www.wa4dsy.net/filter/filterdesign.html The thing to understand about these BASIC_RX cards is that they're just designed for direct-sampling into the ADCs.
List: time-nuts@lists.febo.com
From: Titan Corp
 
RE: [time-nuts] PTTI
Fri, Aug 12, 2005 9:08 PM
This base time of Nov. 17, 1858 has since been used by TOPS-10, TOPS-20, and VAX/VMS.
List: trawlers@lists.trawlering.com
From: LaBomba182@aol.com
 
Good Question!
Thu, Jan 13, 2005 2:16 PM
The wave top is breaking apart and mixing with the air to form foam. Or, The wave top is breaking apart and mixing with the air to form marsh mellow fluff. :-) Capt. Bill
List: trawlers@lists.trawlering.com
From: Tom Collier
 
Re: T&T: Trawler pilot house doors
Mon, Oct 17, 2016 1:00 PM
2 coats of original to match the color then clear gloss on top. It holds up well. Just keep up with it. Tom Sent from my iPhone > On Oct 16, 2016, at 6:59 AM, Bob wrote: > > Tom, > > How did the Cetol hold up on top of the epoxy. Which flavor did you use? > > Bob