List: usrp-users@lists.ettus.com
From: Peter Janhäll
Re: [USRP-users] FPGA hack newbie problems
Thu, Jul 19, 2012 8:29 PM
in the Doxygen database.
Regards
Peter J
2012/7/19 Nick Foster
> On Thu, Jul 19, 2012 at 2:48 AM, Peter Janhäll wrote:
>
>> Hello everyone,
>> I have an E100 capable of sampling at 21 MHz (according to itself), but I
>> need to sampla at atleast 60 MHz.
>> There is no need for continous sampling at this speed, the goal is to
>> find the dominating frequency which is fairly stable.
>>
>> I need help/info/suggestions on:
>> 1) Where in the dataflow of the FPGA is it possible (least risk/work) to
>> do this re-packing of the ADC stream?
>>
>
> I suggest you start by looking at the custom/ directory in the UHD fpga
> source, specifically custom_dsp_rx.v and custom_engine_rx.v. We've
> implemented the ability to compile custom modules which can be used for
> this sort of thing.
>
>
>> 2) Is the FPGA cruicial to the operation of the E100 (will it die with
>> the FPGA)? Or will a rotten FPGA image just spoil the sampling ability?
>>
>
> The latter. The processing is all on the Gumstix Overo board. The FPGA is
> used exclusively for DSP-related tasks. However, it's possible a bad FPGA
> image could stomp on the GPMC bus shared with the Ethernet controller and
> gum up your Ethernet connection.
>
>
>> 3) Where do I put the FPGA configuration file, and in what format, to
>> have it loaded into the FPGA?
>>
>
> You can specify that in the UHD source/sink arguments. I.e.:
>
> wat = uhd.single_usrp_source("fpga=my_fpga_image.bin",
> uhd.io_type_t.COMPLEX_FLOAT32, 1)
>
> The examples included with UHD pass args in via the --args parameter, so
> you can say:
>
> rx_samples_to_file --args=fpga=my_fpga_image.bin
>
> --n
>
>
>> Kind regards
>> Peter J
>>
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>>
>>
>