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List: birdalert@ontbirds.ca
From: Fazio Luke
 
[Ontbirds] Marbled Godwit is back at Niagara, Video https://youtu.be/t2ZaSeGPoOs
Fri, Aug 23, 2019 3:29 PM
https://youtu.be/t2ZaSeGPoOs Hi folks:  The friendly MARBLED GODWIT has returned to Dufferin Islands in Niagara Falls. https://youtu.be/t2ZaSeGPoOs MAGO.. seems to be friendly. It interacts well with the many Mallards, but seems to be attacked by RB Gulls occasionally.Best of luck this weekend.
List: pjsip@lists.pjsip.org
From: David Villasmil Govea
 
Re: [pjsip] Web RTC Support
Fri, Sep 11, 2015 11:22 AM
What we needed was to you use pjsip as a proxy > between the client and the SIP Server: > > jssip (Client) <-------> (WebRTC) pjsip (SIP) <----------> OpenSIPS > > Terrance > ​ > > _______________________________________________ > Visit our blog: http://blog.pjsip.org > > pjsip mailing list > pjsip@lists.pjsip.org > http://lists.pjsip.org/mailman/listinfo/pjsip_lists.pjsip.org
List: time-nuts@lists.febo.com
From: Tom Van Baak
 
Re: [time-nuts] Environmental sensor recommendations
Thu, Apr 5, 2018 9:21 PM
PCB and flex boards: https://store.digilentinc.com/pmod-tmp2-temperature-sensor/ http://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-adt7420.html /tvb
List: websecurity@lists.webappsec.org
From: Hani Benhabiles
 
Re: [WEB SECURITY] How secure is Drupal?
Mon, Oct 31, 2011 4:35 PM
.**** >> >> Would you go for Drupal as your web app? Or you might have some security >> considerations on this regard?
List: usrp-users@lists.ettus.com
From: Nick Foster
 
Re: [USRP-users] FPGA hack newbie problems
Thu, Jul 19, 2012 5:01 PM
tions on: > 1) Where in the dataflow of the FPGA is it possible (least risk/work) to > do this re-packing of the ADC stream? > I suggest you start by looking at the custom/ directory in the UHD fpga source, specifically custom_dsp_rx.v and custom_engine_rx.v. We've implemented the ability to compile custom modules which can be used for this sort of thing. > 2) Is the FPGA cruicial to the operation of the E100 (will it die with the > FPGA)? Or will a rotten FPGA image just spoil the sampling ability? > The latter. The processing is all on the Gumstix Overo board. The FPGA is used exclusively for DSP-related tasks. However, it's possible a bad FPGA image could stomp on the GPMC bus shared with the Ethernet controller and gum up your Ethernet connection. > 3) Where do I put the FPGA configuration file, and in what format, to have > it loaded into the FPGA? > You can specify that in the UHD source/sink arguments. I.e.: wat = uhd.single_usrp_source("fpga=my_fpga_image.bin", uhd.io_type_t.COMPLEX_FLOAT32, 1) The examples included with UHD pass args in via the --args parameter, so you can say: rx_samples_to_file --args=fpga=my_fpga_image.bin --n > Kind regards > Peter J > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > >
List: usrp-users@lists.ettus.com
From: Peter Janhäll
 
Re: [USRP-users] FPGA hack newbie problems
Thu, Jul 19, 2012 8:29 PM
in the Doxygen database. Regards Peter J 2012/7/19 Nick Foster > On Thu, Jul 19, 2012 at 2:48 AM, Peter Janhäll wrote: > >> Hello everyone, >> I have an E100 capable of sampling at 21 MHz (according to itself), but I >> need to sampla at atleast 60 MHz. >> There is no need for continous sampling at this speed, the goal is to >> find the dominating frequency which is fairly stable. >> >> I need help/info/suggestions on: >> 1) Where in the dataflow of the FPGA is it possible (least risk/work) to >> do this re-packing of the ADC stream? >> > > I suggest you start by looking at the custom/ directory in the UHD fpga > source, specifically custom_dsp_rx.v and custom_engine_rx.v. We've > implemented the ability to compile custom modules which can be used for > this sort of thing. > > >> 2) Is the FPGA cruicial to the operation of the E100 (will it die with >> the FPGA)? Or will a rotten FPGA image just spoil the sampling ability? >> > > The latter. The processing is all on the Gumstix Overo board. The FPGA is > used exclusively for DSP-related tasks. However, it's possible a bad FPGA > image could stomp on the GPMC bus shared with the Ethernet controller and > gum up your Ethernet connection. > > >> 3) Where do I put the FPGA configuration file, and in what format, to >> have it loaded into the FPGA? >> > > You can specify that in the UHD source/sink arguments. I.e.: > > wat = uhd.single_usrp_source("fpga=my_fpga_image.bin", > uhd.io_type_t.COMPLEX_FLOAT32, 1) > > The examples included with UHD pass args in via the --args parameter, so > you can say: > > rx_samples_to_file --args=fpga=my_fpga_image.bin > > --n > > >> Kind regards >> Peter J >> >> _______________________________________________ >> USRP-users mailing list >> USRP-users@lists.ettus.com >> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >> >> >
List: usrp-users@lists.ettus.com
From: Josh Blum
 
Re: [USRP-users] FPGA hack newbie problems
Thu, Jul 19, 2012 9:13 PM
USTOM_SRCS ./top/N2x0/Makefile.N200R3:CUSTOM_SRCS = ./top/N2x0/Makefile.N200R4:CUSTOM_SRCS = ./top/N2x0/Makefile.N210R3:CUSTOM_SRCS = ./top/N2x0/Makefile.N210R4:CUSTOM_SRCS = ./top/USRP2/Makefile:CUSTOM_SRCS = ./top/E1x0/Makefile.E110:CUSTOM_SRCS = ./top/E1x0/Makefile.E100:CUSTOM_SRCS = ./top/B100/Makefile.B100:CUSTOM_SRCS = Just make a copy of the makefile for you design and set CUSTOM_SRCS with a list of paths to your new verilog files. A possible example of setting such a variable, you might look here: http://code.ettus.com/redmine/ettus/projects/uhd/repository/revisions/master/entry/fpga/usrp2/fifo/Makefile.srcs#L8 > 3) Is the FPGA reconfigured for each call of uhd::usrp::multi_usrp::make() > ? Does this explain the start delay? The FPGA configuration is very fast on E100. I think you are seeing delay of clock configuration and check for lock, and even more so, the timeout looking for GPSDO. I will be pushing code soon to the next branch where the E100 caches the result of looking for the GPSDO so it doesnt look every time. > I couldn't find the single_usrp_source() in the Doxygen database. > The source and sink blocks are gnuradio wrappers http://gnuradio.org/cgit/gnuradio.git/tree/gr-uhd/include/ And this is the doxygen page for the UHD API: http://files.ettus.com/uhd_docs/doxygen/html/classuhd_1_1usrp_1_1multi__usrp.html -josh
List: discuss@lists.openscad.org
From: OzAtMichael
 
Re: [OpenSCAD] trouble setting up https://github.com/adrianschlatter/threadlib
Fri, May 15, 2020 12:26 AM
There are a few string handling libraries, such as https://www.thingiverse.com/thing:526023 https://github.com/revarbat/BOSL2/wiki/strings.scad ("BOSL2 IS PRE-ALPHA CODE.
List: discuss@lists.openscad.org
From: Bruno Boettcher
 
Re: [OpenSCAD] trouble setting up https://github.com/adrianschlatter/threadlib
Fri, May 15, 2020 12:47 PM
> > > > There are a few string handling libraries, such as > > https://www.thingiverse.com/thing:526023 > > https://github.com/revarbat/BOSL2/wiki/strings.scad > > ("BOSL2 IS PRE-ALPHA CODE.
List: websecurity@lists.webappsec.org
From: Oussama Gabi
 
[WEB SECURITY] Numeric SQL injection ASP.NET
Mon, Apr 25, 2011 12:15 PM
Hello guys, I am a beginner in web application Security, so I started to train on webgoat.i would like to make numeric SQL injection attack but in ASP.net. So I created a dropdownlist that retrieves the names of cities and a gridview for display! The problem is when I change the ID value with tamperdata, nothing happens.