# General parameters
# -----------------------------------------
schema: rfnoc_imagebuilder_args         # Identifier for the schema used to validate this file
copyright: >-                           # Copyright information used in file headers
  Copyright 2024 Admin Research
license: >-                             # License information used in file headers
  SPDX-License-Identifier: do What The F*ck you want to Public License
version: '1.0'                          # File version (must be string so we can distinguish 1.1 and 1.10)
chdr_width: 64                          # Bit width of the CHDR bus for this image
device: 'x310'
default_target: 'X310_XG'

# A list of all stream endpoints in design
# ----------------------------------------
stream_endpoints:
  ep_radio0_ddc00:                                  # Stream endpoint name
    ctrl: True                          # Endpoint passes control traffic
    data: True                          # Endpoint passes data traffic
    buff_size: 32768                    # Ingress buffer size for data
  ep_radio0_ddc01:
    ctrl: False
    data: True
    buff_size: 0

  ep_keepn0:
    ctrl: True
    data: True
    buff_size: 32768


  ep_radio1_ddc10:                                  # Stream endpoint name
    ctrl: True                          # Endpoint passes control traffic
    data: True                          # Endpoint passes data traffic
    buff_size: 32768

  ep_radio1_ddc11:
    ctrl: False
    data: True
    buff_size: 0


# A list of all NoC blocks in design
# ----------------------------------
noc_blocks:

  # 1st TwinRx
  ddc00:
    block_desc: 'ddc.yml'     # DDC for radio0,0
    parameters:
      NUM_PORTS: 1

  ddc01:
    block_desc: 'ddc.yml'     # DDC for radio0,1
    parameters:
      NUM_PORTS: 1

  radio0:
    block_desc: 'radio.yml'   # radio 0,0 and 0,1
    parameters:
      NUM_PORTS: 1

  # 2nd TwinRx
  ddc10:
    block_desc: 'ddc.yml'    # DDC for radio1,0
    parameters:
      NUM_PORTS: 1

  ddc11:
    block_desc: 'ddc.yml'     # DDC for radio1,1
    parameters:
      NUM_PORTS: 1

  radio1:
    block_desc: 'radio.yml'   # radio 1,0 and 1,1
    parameters:
      NUM_PORTS: 1

  # processing blocks

  split0:
    block_desc: 'split_stream.yml'
    parameters:
      NUM_PORTS: 1
      NUM_BRANCHES: 2

  keepn0:
    block_desc: 'keep_one_in_n.yml'
    parameters:
      NUM_PORTS: 1
      WIDTH_N: 30        #Bit width of N param (must be <= 31)

  windw0:
    block_desc: 'window.yml'
    parameters:
      NUM_PORTS: 1
      MAX_WINDOW_SIZE: 2048   # 16384 = 2^14 possible with FFT or window ? or FFT size max 2048 (based on doc) ?)  

  fft0:
    block_desc: 'fft_1x64.yml'
    parameters:
      EN_MAGNITUDE_OUT: 0    # enable CORDIC based magnitude output support
      EN_MAGNITUDE_APPROX_OUT: 1  # enable multiplier- less magnitude calc ?
      EN_MAGNITUDE_SQ_OUT: 0   # enable mag sqrt
      EN_FFT_SHIFT: 1      # enable shift 

  logpwr0:
    # computes and estimate 1024 * log2 sqrt(I**2 + Q**2). only 1024 ? and input must be complex and cant be 
    #  mag sqrt output from FFT ?   
    block_desc: 'logpwr.yml'
    parameters:
      NUM_PORTS: 1
      RANDOM_MODE: 0     # 2'b11 in logpwr.yml ??? so  enable random LSBs on each input 0

  s01_ddc1:
    block_desc: 'ddc.yml'
    parameters:
      NUM_PORTS: 1







  windw1:
    block_desc: 'window.yml'
    parameters:
      NUM_PORTS: 1
      MAX_WINDOW_SIZE: 2048   # 16384 = 2^14 possible with FFT or window ? or FFT size max 2048 (based on doc) ?)  

  fft1:
    block_desc: 'fft_1x64.yml'
    parameters:
      EN_MAGNITUDE_OUT: 0    # enable CORDIC based magnitude output support
      EN_MAGNITUDE_APPROX_OUT: 1  # enable multiplier- less magnitude calc ?
      EN_MAGNITUDE_SQ_OUT: 0   # enable mag sqrt
      EN_FFT_SHIFT: 1      # enable shift 

  logpwr1:
    # computes and estimate 1024 * log2 sqrt(I**2 + Q**2). only 1024 ? and input must be complex and cant be 
    #  mag sqrt output from FFT ?   
    block_desc: 'logpwr.yml'
    parameters:
      NUM_PORTS: 1
      RANDOM_MODE: 0     # 2'b11 in logpwr.yml ??? so  enable random LSBs on each input 0









# A list of all static connections in design
# ------------------------------------------
# Format: A list of connection maps (list of key-value pairs) with the following keys
#   - srcblk  = Source block to connect
#   - srcport = Port on the source block to connect
#   - dstblk  = Destination block to connect
#   - dstport = Port on the destination block to connect
connections:
  # RF twinRX0 ch 0
  - { srcblk: radio0, srcport: out_0, dstblk: ddc00, dstport: in_0 }
  - { srcblk: ddc00, srcport: out_0, dstblk: split0, dstport: in_0 }

  # RF processing twinRX0 ch0
  - { srcblk: split0, srcport: out_0, dstblk: keepn0, dstport: in_0 }
  - { srcblk: keepn0, srcport: out_0, dstblk: windw0, dstport: in_0 }
  - { srcblk: windw0, srcport: out_0, dstblk: fft0,   dstport: in_0 }
  - { srcblk: fft0, srcport: out_0, dstblk: logpwr0, dstport: in_0 }
  - { srcblk: logpwr0, srcport: out_0, dstblk: ep_keepn0, dstport: in0 }

  - { srcblk: split0, srcport: out_1, dstblk: s01_ddc1, dstport: in_0 }
  - { srcblk: s01_ddc1, srcport: out_0, dstblk: ep_radio0_ddc00, dstport: in0 }


  # RF twinRX0 ch 1
  - { srcblk: radio0, srcport: out_0, dstblk: ddc01,   dstport: in_0 }
  - { srcblk: ddc01, srcport: out_0, dstblk: ep_radio0_ddc01, dstport: in0 }

  ### if some processing added: will this handle changing fc fast (scanner)?

  # RF twinRX1 ch 0
  - { srcblk: radio1, srcport: out_0, dstblk: ddc10, dstport: in_0 }
  - { srcblk: ddc10, srcport: out_0, dstblk: windw1, dstport: in_0 }

  # RF processing twinRX1 ch0
  - { srcblk: windw1, srcport: out_0, dstblk: fft1,   dstport: in_0 }
  - { srcblk: fft1, srcport: out_0, dstblk: logpwr1, dstport: in_0 }
  - { srcblk: logpwr1, srcport: out_0, dstblk: ep_radio1_ddc10, dstport: in0 }


  # RF twinRX1 ch 1
  - { srcblk: radio1, srcport: out_0, dstblk: ddc11,   dstport: in_0 }
  - { srcblk: ddc11, srcport: out_0, dstblk: ep_radio1_ddc11, dstport: in0 }

  ### if some processing added: will this handle static fc (scanner) ?


  #
  # BSP Connections
  - { srcblk: radio0,   srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio0 }
  - { srcblk: radio1,   srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio1 }
  - { srcblk: _device_, srcport: radio0,   dstblk: radio0,   dstport: radio           }
  - { srcblk: _device_, srcport: radio1,   dstblk: radio1,   dstport: radio           }
  - { srcblk: _device_, srcport: time,     dstblk: radio0,   dstport: time            }
  - { srcblk: _device_, srcport: time,     dstblk: radio1,   dstport: time            }

# A list of all clock domain connections in design
# ------------------------------------------------
# Format: A list of connection maps (list of key-value pairs) with the following keys
#   - srcblk  = Source block to connect (Always "_device"_)
#   - srcport = Clock domain on the source block to connect
#   - dstblk  = Destination block to connect
#   - dstport = Clock domain on the destination block to connect
clk_domains:
    - { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio }
    - { srcblk: _device_, srcport: ce,    dstblk: ddc00,   dstport: ce    }
    - { srcblk: _device_, srcport: ce,    dstblk: ddc01,   dstport: ce    }

    - { srcblk: _device_, srcport: radio, dstblk: radio1, dstport: radio }
    - { srcblk: _device_, srcport: ce,    dstblk: ddc11,   dstport: ce    }
    - { srcblk: _device_, srcport: ce,    dstblk: ddc10,   dstport: ce    }
    - { srcblk: _device_, srcport: ce,    dstblk: s01_ddc1,   dstport: ce    }



    - { srcblk: _device_, srcport: ce,    dstblk: keepn0,   dstport: ce    }
    - { srcblk: _device_, srcport: ce,    dstblk: windw0,   dstport: ce    }
    - { srcblk: _device_, srcport: ce,    dstblk: fft0,   dstport: ce    }
    - { srcblk: _device_, srcport: ce,    dstblk: logpwr0,   dstport: ce    }
    - { srcblk: _device_, srcport: ce,    dstblk: windw1,   dstport: ce    }
    - { srcblk: _device_, srcport: ce,    dstblk: fft1,   dstport: ce    }
    - { srcblk: _device_, srcport: ce,    dstblk: logpwr1,   dstport: ce    }
