import logging
import sys
import os
sys.path.append(os.path.dirname(__file__) + '/..')
sys.path.append('/usr/lib/python3/dist-packages/')
import uhd
import numpy as np
import argparse
import time

def main():
    parser = argparse.ArgumentParser()
    # Per USRP-users list, time_source/clock_source recommended in args, possibly in addition to in code
    # It's assumed FPGA is already running WX (White Rabbit flavor) and WR switch is running
    parser.add_argument("-a", "--args", default="name=SDR2,time_source=sfp0,clock_source=internal", type=str)
    args = parser.parse_args()

    usrp = uhd.usrp.MultiUSRP(args.args)
    usrp.set_clock_source("internal")
    usrp.set_time_source("sfp0",0)

    while True:
        for mboard_idx in range(usrp.get_num_mboards()):

            logging.info('\nmboard[%d] time_synchronized: %s, Clock Source: %s, Time Source: %s', mboard_idx, usrp.get_time_synchronized(),
                         usrp.get_clock_source(mboard_idx), usrp.get_time_source(mboard_idx) )
            mboard_time = usrp.get_time_now(mboard_idx)
            logging.info('mboard[%d] time_now -- %.15lfs (%s)', mboard_idx, mboard_time.get_real_secs(),
                            time.strftime('%a, %d %b %Y %H:%M:%S +0000', time.gmtime(mboard_time.get_real_secs())))

            mboard_time_last_pps = usrp.get_time_last_pps(mboard_idx)
            logging.info('mboard[%d] time_last_pps -- %.15lfs (%s)', mboard_idx, mboard_time_last_pps.get_real_secs(),
                            time.strftime('%a, %d %b %Y %H:%M:%S +0000', time.gmtime(mboard_time_last_pps.get_real_secs())))

        time.sleep(1)

if __name__ == "__main__":
    logging.basicConfig(format='%(asctime)s [%(levelname)s]: %(message)s', level=logging.DEBUG)
    main()